Baya - Auto Integration of SoC Components with IP-XACT & Tcl API
This tool takes the Verilog RTL file(s) along with other options including defines if any and writes out the preprocessed verilog file(s). This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file which can be directly used from the 'lib' directory in the downloaded tar or ZIP file. Example-
source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
If you do not use the -out switch then the result will be dumped in a directory name VlogPP inside the run directory.
If you have multiple input files then list all of those in a startup file provide that startup file with -f switch instead of -in switch and do not specify the output file name. All the preprocessed files will be written inside the dir named 'VlogPP' in the run directory.
Go through the examples to get a better understanding of this tool. The examples are pretty comprehensive and covers wide range of possible scenario. Send mails to help@edautils.com if you need any assistance.
Go to the installation directory i.e the directory where this README file resides and run the runme.csh script.
Get details by executing it as 'preprocessverilog -help'