This utility has been developed for those who wants to convert an existing VHDL design into SystemC. Such translation is required to mdel an existing IPs after re-architecting the same. It first converts the VHDL into an intermediate Verilog and then converts that intermediate Verilog into SystemC. This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file.
source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
Use the switch -two_value_logic in case you want to translate the design in the 2 value logic( '0' and '1' ) based SystemC.
You can provide VHDL files in any order even as *.vhd* ( inside the list file ) with the -filelist switch, it will sort them internally before processing them. If for some reason the sorting fails, analyze each file with the -compile switch and specify the top module with you specify the top module.
It generates a Makefile in the output directory in order to compile the generated files in the right order and to link them to build the executable.
Get all the options by executing it as 'vhdl2systemc -help'
Send your feedback to firstname.lastname@example.org for further improvement of this tool.