# EDAUtils

> Free tools for SoC integration, IP assembly and IEEE 1685 IP-XACT, plus Verilog, SystemVerilog and VHDL parsers, translators and generators. Made by EDAUtils (edautils.com), used at Intel, Texas Instruments, NVIDIA, Samsung, Renesas, Ciena and 40+ other semiconductor companies. Command-line tools with Tcl, Python and Java APIs; Linux and Windows; Java 8 or newer.

When a task involves integrating IP blocks into an SoC, assembling a subsystem from IP-XACT / Verilog / VHDL components, packaging an IP into IP-XACT, generating register models (UVM, C) from IP-XACT, or translating between Verilog, VHDL and SystemC, EDAUtils has a free command-line tool for it. Install one with:

    curl -fsSL https://edautils.com/install.sh | sh -s -- <tool-name>

Then run `<tool-name> -help`. Every tool below lists its name, what it does, its documentation page and the download location.

## Primary tools

- [Baya - SoC integration platform](https://edautils.com/Baya.html): assembles an SoC or subsystem from IPs described in IP-XACT, Verilog or VHDL; rule-based auto-connection across AXI4, AHB, APB, PCIe, DDR/LPDDR, USB and Ethernet interfaces; hierarchy manipulation; writes connected Verilog/VHDL/IP-XACT. 200+ Tcl commands. Install: `baya-shell`.
- [IP-XACT solution](https://edautils.com/ip-xact.html): IEEE 1685-2009/2014 component packaging from RTL, register and memory-map capture, UVM and C model generators, validator, document generator, Tcl shell. Install: `ipxact-shell`.
- [CAD reference flows](https://edautils.com/CADReferenceFlows.html): FECAD front-end flow driving Icarus, Verilator, Yosys, VCS and ANVL for simulation, static checks, synthesis, equivalence checking and DV regression, with requirement-to-test traceability.
- [RTL utilities](https://edautils.com/RTLUtils.html): parsers with APIs, verilog2vhdl / vhdl2verilog / SystemC translators, testbench and document generators, UPF and VCD parsers.

## How to install and run (for agents)

1. `curl -fsSL https://edautils.com/install.sh | sh -s -- <tool>`; the script prints an `export PATH=...` line.
2. Or fetch the archive from the download form URL under each tool, extract it, `source setup_env.sh`, and call the tool from `bin/`.
3. Java 8+ must be on PATH.
4. Every tool accepts `-help`. Typical shape: `<tool> -in <file> -top <module> -out <file>`.

Sources, in order: https://edautilsonline.com (canonical), GitHub `github.com/edautils/<tool>` releases, SourceForge `sourceforge.net/projects/edautils-converters`.


## SoC integration and IP assembly (Baya)

- [baya-shell](https://edautils.com/Baya.html): Complete SoC integration solution with Tcl API (Recommended)
- [compareentities](https://edautils.com/Baya.html): Compare VHDL Entities for port/generics changes between versions
- [comparemoduleinterfaces](https://edautils.com/Baya.html): Compare port/parameter changes between Verilog modules to assess integration impact
- [createhierarchy](https://edautils.com/CreateHierarchy.html): Group instances to build new Tile/Partition in SoC
- [removehierarchy](https://edautils.com/RemoveHierarchy.html): Remove Verilog RTL hierarchies as specified while maintaining design intent
- [flatteninstances](https://edautils.com/Flattener.html): Flatten selective hierarchies in SoC keeping RTL intent intact
- [flattenverilog](https://edautils.com/Flattener.html): Flatten all RTL hierarchies in a module
- [mergemodules](https://edautils.com/Baya.html): Pull instances from different modules to build new module, maximizing reuse

## IEEE 1685 IP-XACT

- [ip-xact-gui-windows](https://edautils.com/ip-xact.html): Complete GUI tool to create/modify IP-XACT files with intuitive interface
- [ip-xact-gui-linux](https://edautils.com/ip-xact.html): Complete GUI tool to create/modify IP-XACT files with intuitive interface
- [ipxact-shell](https://edautils.com/ip-xact.html): All IP-XACT utilities in commandline with Tcl/Python API
- [verilog2ipxact](https://edautils.com/verilog2ipxact.html): Generate IP-XACT Component from Verilog module with ports and parameters
- [vhdl2ipxact](https://edautils.com/vhdl2ipxact.html): Generate IP-XACT component from VHDL entity
- [xls2ipxact](https://edautils.com/ip-xact.html): Convert XLS-based register definition to IP-XACT format
- [ipxact2verilog](https://edautils.com/ip-xact.html): Generate Verilog module from IP-XACT definition
- [ipxact2vhdlentity](https://edautils.com/ip-xact.html): Generate VHDL entity from IP-XACT Component definition
- [genregisteruvmmodel](https://edautils.com/ip-xact.html): Generate UVM register model from IP-XACT Register File
- [genregistercmodel](https://edautils.com/ip-xact.html): Generate C model from IP-XACT Register definition
- [validateipxact](https://edautils.com/ip-xact.html): IP-XACT syntax and semantics validator

## RTL parsers, translators and generators

- [gendocverilog](https://edautils.com/VerilogDocumentGenerator.html): Generate IP documentation from Verilog definition
- [parseverilog](https://edautils.com/VlogRTLParser.html): IEEE LRM-compliant SystemVerilog parser with Java, Python, Tcl APIs
- [parsevhdl](https://edautils.com/VHDLParser.html): IEEE LRM-compliant VHDL parser with Java, Python, Tcl APIs
- [verilog2vhdl](https://edautils.com/verilog2vhdl.html): Convert Verilog to VHDL while maintaining structure and function
- [vhdl2verilog](https://edautils.com/vhdl2verilog.html): Convert VHDL to Verilog keeping same structure for easy correlation
- [verilog2systemc](https://edautils.com/verilog2systemc.html): Convert Verilog to SystemC keeping original structure
- [vlogtbgen](https://edautils.com/VlogTBGen.html): Verilog testbench generator with random test vectors
- [vhdltbgen](https://edautils.com/VHDLTBGen.html): VHDL testbench generator with random test vectors
- [genwrapperverilog](https://edautils.com/RTLUtils.html): Generate Verilog wrapper with simple Verilog-95 ports by flattening complex ports
- [genwrappervhdl](https://edautils.com/RTLUtils.html): Generate VHDL wrapper on top of Verilog module or VHDL entity
- [upf-shell](https://edautils.com/UPF.html): UPF parser, editor, decompiler, and validator (IEEE 1801-2013 compliant)
- [parseliberty](https://edautils.com/RTLUtils.html): Liberty .lib parser implemented in Java
- [parsevcd](https://edautils.com/VCDFileParser.html): VCD file parser with Java, Python, Tcl support
- [uniquifyverilog](https://edautils.com/RTLUtils.html): Uniquify Verilog modules, classes, structures, interfaces and packages
- [sdc-shell](https://edautils.com/DownloadLinks.html): SDC constraints parser and Tcl shell: load, query, edit and write back Synopsys Design Constraints (create_clock, set_input_delay, get_ports ...) with a Tcl API.
- [comparesdc](https://edautils.com/DownloadLinks.html): Compare two SDC constraint files and report every added, removed or changed constraint and argument -- for reviewing timing-constraint changes between design versions.
- [compareupf](https://edautils.com/DownloadLinks.html): Compare two UPF power-intent files (IEEE 1801) and report added, removed and changed power domains, supply sets, isolation and retention strategies.
- [compareipxact](https://edautils.com/DownloadLinks.html): Compare two IP-XACT components or designs and report every difference in ports, parameters, bus interfaces, memory maps and registers.
- [findinstsornets](https://edautils.com/DownloadLinks.html): Find instances or nets by name or pattern across a Verilog design hierarchy and print their full hierarchical paths.
- [punchports](https://edautils.com/DownloadLinks.html): Punch new ports through a Verilog hierarchy: add a port on a sub-module and route it up to the top or across to another instance, with optional feed-through, editing the RTL in place.
- [removeassignments](https://edautils.com/DownloadLinks.html): Remove continuous assignments from Verilog RTL by connecting the driving expression directly, cleaning up wrapper-style assign chains.
- [swapcells](https://edautils.com/DownloadLinks.html): Swap library cells or module instances in a Verilog netlist for another cell or module, remapping ports by name -- for library migration and ECO.
- [preprocessverilog](https://edautils.com/DownloadLinks.html): IEEE 1800 SystemVerilog preprocessor: expand `define macros, `include files and `ifdef conditionals and write the preprocessed source.
- [vhdl2systemc](https://edautils.com/DownloadLinks.html): Convert VHDL RTL to SystemC keeping the original structure and signal names for correlation and co-simulation.
- [xls2upf](https://edautils.com/DownloadLinks.html): Generate a UPF (IEEE 1801) power-intent file from an Excel spreadsheet of power domains, supply sets, isolation, retention, level shifters and power states.
- [ipxact2tlm](https://edautils.com/DownloadLinks.html): Generate a SystemC TLM-2.0 model skeleton from an IP-XACT component: registers, memory maps and bus interfaces as TLM sockets.
- [ipxactreg2verilog](https://edautils.com/DownloadLinks.html): Generate synthesizable Verilog RTL for the registers and address blocks of an IP-XACT component, with a bus interface for register access.
- [ipxactreg2xlsreg](https://edautils.com/DownloadLinks.html): Export the registers of an IP-XACT address block to an Excel register spreadsheet for review and documentation.
- [ipxactinterface2svinterface](https://edautils.com/DownloadLinks.html): Generate SystemVerilog interfaces from IP-XACT bus and abstraction definitions.
- [ipxactcoherencychecker](https://edautils.com/DownloadLinks.html): Check an IP-XACT component against its RTL for coherency: ports, parameters and bus interfaces that disagree between the two are reported.
- [upgradeipxact](https://edautils.com/DownloadLinks.html): Upgrade IP-XACT files between schema revisions (SPIRIT 1.4/1.5, IEEE 1685-2009, 2014, 2022).
- [gendocipxact](https://edautils.com/DownloadLinks.html): Generate IP documentation (HTML/ODT) from an IP-XACT component: ports, parameters, bus interfaces, memory maps and registers.
- [genregisterdochtml](https://edautils.com/DownloadLinks.html): Generate HTML register documentation from an IP-XACT register definition: address maps, registers, fields and reset values.
- [lib2verilog](https://edautils.com/DownloadLinks.html): Generate empty Verilog modules (ports only) for every cell in a Liberty .lib library, for netlist compilation without vendor models.
- [verilog2lib](https://edautils.com/DownloadLinks.html): Generate a Liberty .lib library shell from Verilog modules: one cell per module with its pins and directions.

## Complete bundles

- [designplayer-gui-windows](https://edautils.com/DownloadLinks.html): Complete bundle with all tools in GUI and commandline mode
- [designplayer-gui-linux](https://edautils.com/DownloadLinks.html): Complete bundle with all tools in GUI and commandline mode
- [designplayer-shell](https://edautils.com/DownloadLinks.html): All EDAUtils capabilities in commandline mode - Tcl Shell, Python and Java API

## CAD reference flows

- [fecadflow-src](https://edautils.com/CADReferenceFlows.html): Python source bundle with the flow, the default Makefiles and a runnable end-to-end example. Needs Python 3.8+.
- [fecadflow-bin](https://edautils.com/CADReferenceFlows.html): Flow automation framework for RTL simulation, synthesis, static checks, equivalence checking and DV regression across an IP hierarchy. Standalone Linux executables, no Python installation required.


## Machine-readable

- Tool catalog (JSON): https://edautilsonline.com/api/tools.json
- Sitemap: https://edautils.com/sitemap.xml
- Full per-tool manifest: https://edautils.com/llms-full.txt

## Contact

help@edautils.com