- What it isSoC integration and IP assembly
- InputsIP-XACT, Verilog, VHDL, SV interfaces, XLS/CSV
- Scripting200+ Tcl commands, Java API
- LicenseFree, no license server
Overview
Modern SoC and FPGA projects assemble hundreds of IP blocks from internal teams, other divisions and commercial IP vendors, across multiple power and voltage domains. IP integration is where that effort and most of the connectivity errors concentrate: thousands of ports wired by hand, and re-wired every time the constraints change.
Baya is a free SoC integration tool for IP assembly in VLSI and SoC design. It assembles subsystems and full SoCs from IPs defined in IP-XACT, Verilog or VHDL, auto-connects AXI4, AHB, APB, PCIe, DDR and custom interfaces by rule, manipulates hierarchy, and writes connected RTL. Its GUI provides Commands, Tool Boxes and a Connection Wizard to import IPs, instantiate components and build connections, and every action maps to Tcl: around 200 high-level Tcl commands and hundreds of low-level APIs for advanced users. See the SoC integration guide for methodology and a comparison with commercial integration tools.
Install and run
These commands come from the examples/ directory in the current release and were run against it.
$ curl -fsSL https://edautils.com/install.sh | sh -s -- baya-shell
$ source $EDAUTILS_ROOT/setup_env.sh
$ baya-shell create_design.tclwith create_design.tcl containing:
baya_set_file -name system1.v
baya_import_verilog_filelist -filelist infile.list -top top
baya_set_current_design -name leaf
baya_create_hierarchy -insts u_grandleaf_1,u_grandleaf_2 \
-new_inst_name u_new_grandleaf -new_mod_name new_grandleaf
baya_set_current_design -name top
baya_remove_hierarchy -inst u_mid_1
puts [baya_print_verilog -module top]Linux and Windows, Java 8 or newer, no license server. Every command accepts -help.
The GUI
Supported standards
| Standard | Versions | Notes |
|---|---|---|
| IP-XACT | IEEE 1685-2009, 1685-2014, 1685-2022 | 1685-2009 is the default output; -v2014 and -v2022 select the newer schemas. SPIRIT 1.4 and 1.5 files are read. |
| Verilog / SystemVerilog | IEEE 1800-2012 grammar; source types 2009, 2012 and 2017 | Covers Verilog-2001 and Verilog-2005 designs. |
| VHDL | VHDL-2002 and VHDL-2008 source types | Entities, architectures, packages and generate statements. |
| UPF | IEEE 1801-2013 | Parser, editor, decompiler and validator (upf-shell). |
Salient Features of Baya
- 200+ high level Tcl commands for SoC platform assembly
- Easy to get started - use verilog2baya tool to convert existing SoC/SS into Baya format
- Supports Adhoc and Interface based connections
- Supports Autoconnections with rule-based connections between component ports
- Maintains a connectivity database with advance queries
- Supports multiple SoC integration methodologies: XLS/CSV based connections, Port-to-Port adhoc connections, IP-XACT and SystemVerilog Interface based connections
- Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with floor planning
- Associate IP-XACT memory maps with SoC component instances to dump C Model for entire design
- Glue-Logic insertion support
- Spare port insertion through hierarchies
- Automatic creation of top module and ports based on specified rules
- Creates empty modules for compile and elaborate checking
- Utility to compare Entities, Modules and IP-XACT Components
- IP-XACT Coherency checker to ensure compliance with RTL
- Tcl commands to save database as VHDL, Verilog and IP-XACT Design
- Reports Design Maturity in terms of % of unconnected ports
- Unix-like commands (ls, cd, rename etc.) to browse design
- Powerful GUI with hierarchical views and drag-drop capabilities
Demo & Tutorials
Customer Testimonials
"The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately and feel right at home. It was straightforward to quickly reproduce a module previously done with a Perl-to-Verilog utility that was hard to use and maintain. The support from Kanai is excellent. He responds quickly and is a pleasure to deal with. Nice work, Kanai!"
"Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated."
"Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. It's flexibility is a key reason we have chosen it for use in our Cloud-based platform."
"Kanai produced an excellent tool set, which is very useful for a complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by a high quality and ease of use. Bridgit IPXACT creator helps us to pack register, bus and module interfaces into a IEEE standard *.xml SPIRIT format to ensure high reusability in the future and protect our investments. I highly recommend using Kanai's products for every system-on-chip manufacturer."
SoC Integration Utilities
Each of these ships as a standalone command as well as a Baya Tcl command.
- createhierarchyGroup instances into a new hierarchy
- removehierarchyUngroup and dissolve hierarchy levels
- Verilog FlattenerFlatten instances or a whole design
- Find Instances or NetsSearch instances and nets across hierarchy
- Remove AssignmentsStrip concurrent assignments from a netlist
- Clock & Reset Tree AnalyzerTrace clock and reset trees