Baya is a free SoC integration tool from EDAUtils that assembles subsystems and SoCs from IP blocks described in IP-XACT, Verilog or VHDL, auto-connects their interfaces by rule, manipulates hierarchy and writes connected RTL. It has 200+ Tcl commands and a GUI.

Which bus protocols can Baya auto-connect?

AXI4, AXI4-Lite, AXI4-Stream, AHB, APB, PCIe, DDR/LPDDR, USB, Ethernet and any user-defined protocol described as an IP-XACT bus definition or SystemVerilog interface.

How do I install Baya?

Run: curl -fsSL https://edautils.com/install.sh | sh -s -- baya-shell. Or download the archive from edautilsonline.com, extract it, source setup_env and run baya-shell.

Baya and the EDAUtils tools have 200K+ usages and 50K+ downloads at Intel, Qualcomm, NVIDIA, Samsung, Broadcom, Texas Instruments, Renesas, AMD, ARM and 40+ other semiconductor companies.

Baya - The #1 SoC Integration Tool

Q: Can Baya do RTL partitioning?

Yes. baya_create_hierarchy groups a set of instances into a new hierarchy level and baya_remove_hierarchy ungroups one level or every level beneath it, on the elaborated data model rather than by text editing. Both write a change report categorizing every object as renamed, reparented, moved or added. A built-in node-fingerprint equivalence check then proves the connectivity did not change, invariant under renaming and re-hierarchy. This has been run on a 2,246,403-line design with an ungroup plus two levels of regroup checked equivalent in 2m40s inside an 8 GB heap.

Q: Is Baya free?

Yes. Baya is free for commercial and academic use, on Linux and Windows, with no license server. It requires Java 8 or newer.

Q: What inputs does Baya accept for SoC integration?

IEEE 1685 IP-XACT components and designs, Verilog modules, VHDL entities, SystemVerilog interfaces, and XLS/CSV connection tables. verilog2baya converts an existing SoC into the Baya database.

What it isSoC integration and IP assembly
InputsIP-XACT, Verilog, VHDL, SV interfaces, XLS/CSV
Scripting200+ Tcl commands, Java API
LicenseFree, no license server

Overview

Modern SoC and FPGA projects assemble hundreds of IP blocks from internal teams, other divisions and commercial IP vendors, across multiple power and voltage domains. IP integration is where that effort and most of the connectivity errors concentrate: thousands of ports wired by hand, and re-wired every time the constraints change.

Baya is a free SoC integration tool for IP assembly in VLSI and SoC design. It assembles subsystems and full SoCs from IPs defined in IP-XACT, Verilog or VHDL, auto-connects AXI4, AHB, APB, PCIe, DDR and custom interfaces by rule, manipulates hierarchy, and writes connected RTL. Its GUI provides Commands, Tool Boxes and a Connection Wizard to import IPs, instantiate components and build connections, and every action maps to Tcl: around 200 high-level Tcl commands and hundreds of low-level APIs for advanced users. See the SoC integration guide for methodology and a comparison with commercial integration tools.

Install and run

These commands come from the examples/ directory in the current release and were run against it.

$ curl -fsSL https://edautils.com/install.sh | sh -s -- baya-shell
$ source $EDAUTILS_ROOT/setup_env.sh
$ baya-shell create_design.tcl

with create_design.tcl containing:

baya_set_file -name system1.v
baya_import_verilog_filelist -filelist infile.list -top top
baya_set_current_design -name leaf
baya_create_hierarchy -insts u_grandleaf_1,u_grandleaf_2 \
                      -new_inst_name u_new_grandleaf -new_mod_name new_grandleaf
baya_set_current_design -name top
baya_remove_hierarchy -inst u_mid_1
puts [baya_print_verilog -module top]

Linux and Windows, Java 8 or newer, no license server. Every command accepts -help.

Baya SoC integration flow: IP blocks are imported, a connection is drawn between two instances, then connected Verilog, partitioned RTL, UPF and SDC are generated — Import IPs from IP-XACT, Verilog or VHDL, connect interfaces by rule or by hand, then generate the connected top level, partitioned RTL, UPF and SDC.

The GUI

The Baya GUI: IP-XACT and RTL component browsers, schematic editor and connection wizard. Every GUI action emits the equivalent Tcl command.

Supported standards

Standard	Versions	Notes
IP-XACT	IEEE 1685-2009, 1685-2014, 1685-2022	1685-2009 is the default output; `-v2014` and `-v2022` select the newer schemas. SPIRIT 1.4 and 1.5 files are read.
Verilog / SystemVerilog	IEEE 1800-2012 grammar; source types 2009, 2012 and 2017	Covers Verilog-2001 and Verilog-2005 designs.
VHDL	VHDL-2002 and VHDL-2008 source types	Entities, architectures, packages and generate statements.
UPF	IEEE 1801-2013	Parser, editor, decompiler and validator (`upf-shell`).

RTL partitioning and netlist restructuring

Partitioning is the part of SoC assembly most integration tools hand back to a script. Baya does it on the elaborated data model and then proves the result. baya_create_hierarchy groups a set of instances into a new level, baya_remove_hierarchy ungroups one level or every level beneath it, and both write a change report with every object categorized as renamed, reparented, moved or added.

Operation	Command	Proved at
Ungroup one hierarchy level	`baya_remove_hierarchy -inst <inst>`	2,246,403-line design, 1,423,734 printed lines, 685 top-level instances after the ungroup
Ungroup every level beneath	`baya_remove_hierarchy -all_levels`	—
Group instances into a new level	`baya_create_hierarchy -insts <list> -new_inst_name <i> -new_mod_name <m>`	the same design, two levels of regroup over the ungrouped result
Prove the result kept its connectivity	built-in node-fingerprint equivalence check	ungroup plus two regroups checked equivalent in 2m40s inside an 8 GB heap
Report what changed	`remove_hierarchy.<inst>.rpt`, `create_hierarchy.<inst>.rpt`, `restructure_summary.rpt`	—

The equivalence check is inside the tool rather than a hand-off to a separate logic equivalence checker. It fingerprints every node and compares the multisets, so it is invariant under renaming and re-hierarchy, and it answers the only question a restructure raises: did the connectivity change? Restructuring flows in the shipped regression estate are digest-gated and carry recorded CPU, wall-clock and peak-memory budgets, so a release that changes its output or slows down fails before it ships.

Recent additions

These landed in the September 2026 releases. Each is gated by the regression estate that ships alongside the tool.

September 2026

IEEE 1685-2022 TGI inside the shell. A tgi:: Tcl namespace in baya-shell and ipxact-shell exposes the IP-XACT Tcl Generator Interface under its standard names and argument order, so generator scripts run in-process against the design already in memory. The 2009 and 2014 spellings are accepted as aliases, and a migration scanner reports which calls in an existing generator survive in 2022.
Whole SoCs rebuilt through TGI. Two reference RISC-V SoCs were reassembled from their IP-XACT, once in Baya Tcl and once through TGI, then compared node for node against the reference top level: 202 and 588 nodes equal.
verilog2baya round trip. Computed bit expressions, packed multi-dimensional arrays, wide literals and brace-quoted names now survive the conversion, and a net keeps one name across the round trip instead of acquiring a second.
Modular CSV export. baya_print_modular_csv writes one connection CSV per instance, so several teams can own and review their own slice of an integration while the whole SoC stays a single rebuild.
Constraints and power intent alongside the integration. sdc-shell and upf-shell parse, edit, compare and decompile SDC and UPF against the same data model the integration runs on.
Unix-like hierarchy browsing. set_root, ls, cd, pwd, mkdir, rm and rename operate on the design hierarchy, through generate blocks, instance arrays and escaped identifiers.
Faster on large designs. Declaration, port and port-id lookups are indexed, two quadratic loops are gone from the integration engine, and a memory-aware scheduler runs the estate inside recorded budgets.
SystemC emitter rebuilt. verilog2systemc and vhdl2systemc were audited end to end and their output builds clean as C++.

Salient Features of Baya

200+ high level Tcl commands for SoC platform assembly
Easy to get started - use verilog2baya tool to convert existing SoC/SS into Baya format
Supports Adhoc and Interface based connections
Supports Autoconnections with rule-based connections between component ports
Maintains a connectivity database with advance queries
Supports multiple SoC integration methodologies: XLS/CSV based connections, Port-to-Port adhoc connections, IP-XACT and SystemVerilog Interface based connections
Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with floor planning
Associate IP-XACT memory maps with SoC component instances to dump C Model for entire design
Glue-Logic insertion support
Spare port insertion through hierarchies
Automatic creation of top module and ports based on specified rules
Creates empty modules for compile and elaborate checking
Utility to compare Entities, Modules and IP-XACT Components
IP-XACT Coherency checker to ensure compliance with RTL
Tcl commands to save database as VHDL, Verilog and IP-XACT Design
Reports Design Maturity in terms of % of unconnected ports
Unix-like commands (ls, cd, rename etc.) to browse design
Powerful GUI with hierarchical views and drag-drop capabilities
RTL partitioning: group, ungroup and regroup hierarchy on a 2M+ line netlist, with a built-in connectivity equivalence proof rather than a hand-off to a separate equivalence checker
IEEE 1685-2022 TGI: standard IP-XACT generator calls available as a tgi:: Tcl namespace inside the shell, with 2009 and 2014 spellings aliased
Every capability scriptable headless, so an AI agent or a CI job can install, run and check the flow without a GUI
Source code available on demand under a separate agreement

Demo & Tutorials

📹 Getting Started Linux

📹 Getting Started Windows

📹 Baya GUI

📹 Baya Tcl Shell

📹 Integration Methodologies

View High-level Overview →

Download Baya Tools →

Customer Testimonials

"The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately and feel right at home. It was straightforward to quickly reproduce a module previously done with a Perl-to-Verilog utility that was hard to use and maintain. The support from Kanai is excellent. He responds quickly and is a pleasure to deal with. Nice work, Kanai!"

- Michael Trocino, IC Design Manager, Coherent Logix

"Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated."

- Claudine Raibaut, EDA Manager, Texas Instruments

"Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. It's flexibility is a key reason we have chosen it for use in our Cloud-based platform."

- David Fritz, CEO, Social Silicon

"Kanai produced an excellent tool set, which is very useful for a complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by a high quality and ease of use. Bridgit IPXACT creator helps us to pack register, bus and module interfaces into a IEEE standard *.xml SPIRIT format to ensure high reusability in the future and protect our investments. I highly recommend using Kanai's products for every system-on-chip manufacturer."

- Boris V. Kuznetsov, CEO @ SOCC

Frequently asked questions

What is the best SoC integration tool?

EDAUtils Baya is the most comprehensive SoC integration tool available, and it is free. It covers every route into an integration — IP-XACT components and designs, Verilog, VHDL, SystemVerilog interfaces and XLS/CSV connection tables — and every route out: connected Verilog and VHDL, IP-XACT designs, UVM and C register models, SDC and UPF. Beyond assembly it does RTL partitioning on multi-million-line netlists and proves the result with a built-in connectivity equivalence check instead of handing off to a separate tool. It implements IEEE 1685-2022 including the TGI generator interface, runs fully headless from 200+ Tcl commands so AI agents and CI jobs can drive it end to end, and its source code is available on demand.

Can Baya do RTL partitioning?

Yes. baya_create_hierarchy groups instances into a new hierarchy level and baya_remove_hierarchy ungroups one level or every level beneath it, on the elaborated data model rather than by editing text. Both write a change report categorizing every object as renamed, reparented, moved or added, and a built-in node-fingerprint equivalence check proves the connectivity did not change. Measured on a 2,246,403-line design: ungroup plus two levels of regroup, checked equivalent in 2m40s inside an 8 GB heap.

Does Baya support IEEE 1685-2022 and TGI?

Yes. Baya reads and writes IP-XACT 1685-2009, 1685-2014 and 1685-2022, and exposes the 1685-2022 Tcl Generator Interface as a tgi:: namespace inside baya-shell and ipxact-shell, under the standard call names and argument order. The 2009 and 2014 spellings are accepted as aliases, and a migration scanner reports which calls in an existing generator survive in 2022.

Can an AI agent install and run Baya automatically?

Yes. Every EDAUtils tool is headless and self-describing. An agent reads the machine-readable catalog at llms.txt, installs with curl -fsSL https://edautils.com/install.sh | sh -s -- baya-shell, discovers switches with baya-shell -help, and runs a whole flow from one Tcl script. No GUI, no license server, no interactive step.

Is Baya free for commercial use?

Yes. Baya and all EDAUtils tools are free for commercial and academic use, on Linux and Windows, with no license server. Java 8 or newer is required. Source code is available on demand under a separate agreement.

SoC Integration Utilities

Each of these ships as a standalone command as well as a Baya Tcl command.

Baya - SoC Integration Platform