Collection of utilities that transform the quality and efficiency of SoC designs by orders of magnitude. Many of these tools are not available from EDA vendors but are essential during design cycles. All applications are highly configurable and available as libraries to meet custom requirements.
Parsers and Generators
SystemVerilog Parser
Complete IEEE LRM-compliant SystemVerilog parser with Java, Python, and Tcl APIs. Parses RTL and populates object model with rich APIs for design information access.
VHDL Parser
IEEE LRM-compliant VHDL parser supporting synthesizable subset with Java, Python, and Tcl APIs. Complete object model with elaboration capabilities.
Verilog Netlist Parser
Specialized netlist parser with elaboration and data model. Includes sample applications and comprehensive API documentation.
Liberty .lib Parser
Java-based Liberty parser supporting widely used constructs. Ideal for tool developers building lib-related applications.
VCD File Parser
Library to parse VCD files, populate datamodel, and access information through APIs. Supports Java, Python, and Tcl.
UPF Editor & Parser
IEEE 1801-2013 compliant UPF 2.3.x parser with smart IDE, color highlighting, content proposal, and Tcl API.
Translators and Converters
verilog2vhdl
Convert Verilog to VHDL while maintaining structure and function for easy correlation. Primarily targeted for Verilog-95 constructs.
vhdl2verilog
Convert VHDL to Verilog keeping same structure. May require manual tuning for complex constructs like nested records.
verilog2systemc
Convert Verilog to SystemC keeping original structure. Generated output requires fine tuning but provides excellent starting point.
vhdl2systemc
Converts VHDL to SystemC via internal Verilog representation. Generated SC requires manual refinement.
verilog2ipxact
Generate IP-XACT Component or Design from Verilog module definition with ports and parameters.
vhdl2ipxact
Generate IP-XACT component definition from VHDL entity with complete interface mapping.
ipxact2verilog
Generate Verilog module from IP-XACT. Supports protocol-based interface generation from register definitions.
ipxact2vhdlentity
Generate VHDL entity from IP-XACT Component definition with complete port and generic mappings.
verilog2lib
Create Liberty .lib library file from Verilog module definition.
lib2verilog
Convert Liberty .lib cells into empty Verilog modules for integration purposes.
Testbench Generators
Verilog Testbench Generator
Generate Verilog testbench for any module with random test vectors. Simple utility for quick validation.
VHDL Testbench Generator
Generate VHDL testbench for any entity with random test vectors. Ideal for learning and quick RTL validation.
Hierarchy Manipulation
createhierarchy
Group instances to build new Tile/Partition in SoC. Supports behavioral RTL, SV Generate, multi-dimensional arrays.
removehierarchy
Remove Verilog RTL hierarchies as specified. Maintains design functionality while flattening structure.
flatteninstances
Flatten selective hierarchies in SoC while keeping RTL intent intact.
flattenverilog
Flatten all RTL hierarchies in module while maintaining design intent.
mergemodules
Pull instances from two SoCs/HMs to build new HM/Tile, maximizing reuse across SoCs.
punchports
Insert new pin deep in hierarchy and pull to top by creating ports in necessary hierarchical paths.
Comparison and Analysis
comparemoduleinterfaces
Compare port and parameter changes between two Verilog modules. Assess integration impact for IP releases.
compareentities
Compare VHDL entities for port or generic changes. Compare between release versions.
ipxactcoherencychecker
Validate consistency between IP-XACT Component and Verilog/VHDL implementation.
Wrapper Generators
genwrapperverilog
Generate Verilog wrapper with simple Verilog-95 ports by flattening complex ports and parameters. Also wraps VHDL entities.
genwrappervhdl
Generate VHDL wrapper on top of Verilog module or VHDL entity with interface conversion.
genemptymodule
Generate empty/blackbox Verilog modules keeping includes, ports, and parameters intact.
Additional Utilities
VHDL/Verilog Sorting
Read files and print sorted list by analyzing dependencies. Supports configurations and mixed HDL.
Verilog PreProcessor
Resolve macros like nested `ifdef, `define for cleaner RTL analysis.
Verilog Document Generator
Generate IP documentation from Verilog definition with hierarchy, registers, ports, and parameters.
uniquifyverilog
Uniquify modules, classes, structures, interfaces, packages by prepending prefix and updating references.
swapcells
Swap Verilog modules, library cells, or memories with another definition.
SDC Constraint Parser
Read SDC Tcl files, populate datamodel by evaluating commands and expressions, compare structures.
All tools available in DesignPlayer bundle
Download RTL UtilitiesEvery RTL utility
Each tool has its own page with usage and examples.
- verilog2vhdlVerilog to VHDL translator
- vhdl2verilogVHDL to Verilog translator
- verilog2systemcVerilog to SystemC converter
- vhdl2systemcVHDL to SystemC converter
- Verilog Testbench GeneratorTestbench with random stimuli
- VHDL Testbench GeneratorTestbench with random stimuli
- Verilog Document GeneratorIP documentation from RTL
- Verilog RTL ParserJava parser API for Verilog/SystemVerilog
- Verilog Netlist ParserJava parser API for gate-level netlists
- Verilog PreprocessorResolve includes, defines and ifdefs
- VHDL ParserJava parser API for VHDL
- UPF Parser & EditorIEEE 1801 power intent
- VCD File ParserJava parser API for VCD waveforms