Free professional tools for SoC integration, IP-XACT, and RTL manipulation
Contains all EDAUtils tools - GUI, commandline, and point tools including Baya, IP-XACT, and RTL utilities in one comprehensive package.
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DesignPlayer GUI (Windows)
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Complete bundle with all tools in GUI and commandline mode
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DesignPlayer GUI (Linux)
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Complete bundle with all tools in GUI and commandline mode
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designplayer-shell
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All EDAUtils capabilities in commandline mode - Tcl Shell, Python and Java API
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SoC integration solution and associated utilities for IP assembly, hierarchy manipulation, and system-level integration.
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baya-shell
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Complete SoC integration solution with Tcl API (Recommended)
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compareentities
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Compare VHDL Entities for port/generics changes between versions
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comparemoduleinterfaces
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Compare port/parameter changes between Verilog modules to assess integration impact
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createhierarchy
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Group instances to build new Tile/Partition in SoC
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removehierarchy
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Remove Verilog RTL hierarchies as specified while maintaining design intent
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flatteninstances
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Flatten selective hierarchies in SoC keeping RTL intent intact
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flattenverilog
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Flatten all RTL hierarchies in a module
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gendocverilog
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Generate IP documentation from Verilog definition
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Complete IP-XACT solution for component packaging, register definition, and design integration.
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IP-XACT GUI (Windows)
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Complete GUI tool to create/modify IP-XACT files with intuitive interface
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IP-XACT GUI (Linux)
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Complete GUI tool to create/modify IP-XACT files with intuitive interface
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ipxact-shell
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All IP-XACT utilities in commandline with Tcl/Python API
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verilog2ipxact
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Generate IP-XACT Component from Verilog module with ports and parameters
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vhdl2ipxact
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Generate IP-XACT component from VHDL entity
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xls2ipxact
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Convert XLS-based register definition to IP-XACT format
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ipxact2verilog
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Generate Verilog module from IP-XACT definition
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ipxact2vhdlentity
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Generate VHDL entity from IP-XACT Component definition
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genregisteruvmmodel
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Generate UVM register model from IP-XACT Register File
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genregistercmodel
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Generate C model from IP-XACT Register definition
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validateipxact
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IP-XACT syntax and semantics validator
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Comprehensive collection of Verilog, VHDL, and UPF tools for modern EDA workflows.
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parseverilog (SystemVerilog)
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IEEE LRM-compliant SystemVerilog parser with Java, Python, Tcl APIs
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parsevhdl
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IEEE LRM-compliant VHDL parser with Java, Python, Tcl APIs
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verilog2vhdl
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Convert Verilog to VHDL while maintaining structure and function
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vhdl2verilog
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Convert VHDL to Verilog keeping same structure for easy correlation
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verilog2systemc
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Convert Verilog to SystemC keeping original structure
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vlogtbgen
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Verilog testbench generator with random test vectors
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vhdltbgen
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VHDL testbench generator with random test vectors
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genwrapperverilog
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Generate Verilog wrapper with simple Verilog-95 ports by flattening complex ports
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genwrappervhdl
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Generate VHDL wrapper on top of Verilog module or VHDL entity
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upf-shell
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UPF parser, editor, decompiler, and validator (IEEE 1801-2013 compliant)
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parseliberty
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Liberty .lib parser implemented in Java
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parsevcd
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VCD file parser with Java, Python, Tcl support
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uniquifyverilog
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Uniquify Verilog modules, classes, structures, interfaces and packages
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mergemodules
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Pull instances from different modules to build new module, maximizing reuse
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Generates Makefiles and drives Icarus, Verilator, Yosys, VCS and ANVL for RTL simulation, synthesis, static checks, equivalence checking and DV regression across a hierarchy of soft-IPs, hard-IPs, VIPs and SoCs. Includes requirement-to-test traceability.
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FECAD Flow (prebuilt binaries)
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The same flow as standalone Linux executables - no Python installation required.
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Need help with installation or setup? Check our FAQ section or watch our video tutorials. For additional support, contact us.