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Tool Category |
Tool Name |
Short Description |
Individual Download Link |
Download Link Table( Jotform ) |
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DesignPlayer |
DesignPlayer GUI ( Windows ) |
Contains all the EDAUtils' tools in commandline mode and also the GUI. This bundle contains all the tools from EDAUtils – both the GUI, commandline and point tools. |
All Download |
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DesignPlayer GUI ( Linux ) |
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designplayer-shell |
Collection of all EDAUtils'capabilities in the commandline mode- point tools, Tcl Shell, Python and Java API. |
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Baya |
baya-shell (Recommend) |
SoC integration solution and associated utilities required for the IP assembly. |
All Download |
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compareentities |
Compare VHDL Entities especially to check if there is any change port or generics. Mostly used to compare same entity's two release versions. |
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comparemoduleinterfaces |
Compare port and parameter changes between two verilog modules. It is often used to assess integration effort impact when a an IP is released to SOC. |
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createhierarchy |
Utility to group instances selectively to build a new Tile/Partition in the SOC. |
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removehierarchy |
Removes Verilog RTL hierarchies as specified by the users. |
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flatteninstances |
Flatten selective hierarchies in the SOC keeping the RTL intent intact. |
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flattenverilog |
Utility to flatten all RTL hierarchies in a module keeping the design intent intact. |
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gendocverilog |
Utility to generate IP documentation from the Verilog definition. |
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genregisterdochtml |
Generate HTML documentation from the IP-XACT Register file. |
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genregistercmodel |
Generate C model from the IP-XACT Register definition. |
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genregisteruvmmodel |
Utility to generate UVM model from the IP-XACT Register File. |
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genwrapperverilog |
Generate Verilog wrapper with simple Verilog-95 ports and parameters on of a SV Verilog module with complex ports and parameters by flattening those. Also, generates wrapper on top of a VHDL entity. |
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genwrappervhdl |
Generates VHDL wrapper on top of a Verilog module or VHDL entity. |
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IP-XACT |
IP-XACT GUI to create/modify(Windows) |
GUI Tool(s) to create IP-XACT files from scratch or update existing IP-XACT file. It's intuitive tool where one can instantiate the bus interfaces based upon existing Bus Definitions and Abstraction Definitions. One can create the Bus/Abstraction Definitions, from the scratch. Address Block/Registers, Vendor Extensions can be created/modified. In fact, almost everything around IP-XACT can be done through the GUI. This bundle also contains the commandline i.e. ipxact-shell which can be used to lower level of automation. |
All Download |
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IP-XACT GUI to create/modify(Linux) |
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ipxact-shell |
Collection of all the IP-XACT related utilities from EDAUtils in the commandline mode. Apart from individual point tools, it supports Tcl and Python based commands/APIs as well. |
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verilog2ipxact |
Generate IP-XACT Component definition from Verilog module definition. It will create the IP-XACT components with ports and parameters. If you need additional constructs like bus-interfaces, memory maps etc. then use the ipxact-shell along with Tcl/Python commands. |
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vhdl2ipxact |
Utility to generate IP-XACT component definition from a VHD entity. |
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xls2ipxact |
Convert XLS based register definition into IP-XACT Register. If your input XLS has different format then provide the column mappings so that tool can understand which column contains relevant register/bit-field information. |
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ipxact2tlm |
Generates TLM model from the IP-XACT definition( alpha release ) |
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ipxact2verilog |
Generate Verilog module from the IP-XACT definition. Also, has capability to generate protocol based interfaces from the register definitions which helps to reuse the IP for multiple protocols. |
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ipxact2vhdlentity |
Generate VHDL entity from the IP-XACT Component definition. |
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genregisterdochtml |
Generate HTML documentation from the IP-XACT Register file. |
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genregistercmodel |
Generate C model from the IP-XACT Register definition. |
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genregisteruvmmodel |
Utility to generate UVM model from the IP-XACT Register File. |
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ipxactcoherencychecker |
Utility to check consistency between IP-XACT Component and Verilog/VHDL implementation of an IP. |
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ipxactinterface2svinterface |
Generate SV interface from the IP-XACT interface( Bus/Abstraction ) definitions. |
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ipxactreg2verilog |
Generate Verilog definition from the IP-XACT register definition, enables slave bus interfaces for the IP corresponding to which the input registers are given. |
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ipxactreg2xlsreg |
Create REGISTER XLS by translating the IP-XACT register definition details. |
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validateipxact – IP-XACT Linting |
IP-XACT Linting solution – checks syntax/semantics of IP-XACT component and Register definition. |
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upgradeipxact |
IP-XACT older version to newer version migration( uses external transformers ), eary release. |
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RTL Utilities |
sdc-shell |
Utility to read SDC file and print out effective commands by resolving Tcl procs, variables etc. |
All Download |
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upf-shell |
UPF parser implemented in Java. Also, utility to read UPF commands buried inside Tcl procs and variables/equations and it decompiles the effective commands. |
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parseliberty |
Liberty .lib parser implemented in Java. Tool developer can use this parser to build relevant application involving .lib reading. |
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parsevcd |
VCD parser implemented in Java( early release ), supports Python and Tcl as well. |
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parseverilog ( SV ) |
SystemVerilog parser implemented with Java which supports Python and Tcl APIs as well- supports all constructs of the IEEE LRM. |
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parsevhdl |
VHDL parser implemented with Java which supports Python and Tcl APIs as well- supports all constructs of the IEEE LRM. |
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preprocessverilog |
Utility to preprocess SystemVerilog file by resolving compiler directives(macro e.g. `define/ìfdef/...). |
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punchports |
Utility to insert a new pin deep in RTL hierarchy and pull that out to the top by inserting pins in the necessary hierarchical paths. |
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mergemodules |
Solution to pull instances( read HMs/Tiles ) from two SoC/HMs and build a new HM/Tile to maximize the reuse across SOCs. Additional details. |
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swapcells |
Swaps verilog module, library cells, memories with another definition of the same |
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uniquifyverilog |
Uniquify SystemVerilog modules, classes, structures, interfaces and packages and their usages in the given IP. |
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removeassignments |
Remove intermediate assignment statements in the Verilog module RTL( alpha release ). |
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verilog2lib |
Create liberty .lib file from the Verilog definition of a module/IP. |
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verilog2systemc |
Generate SystemC definition of an IP from its existing Verilog implementation. It is useful when an IP is planned for re-implement/re-architecture. The generated output requires fie tuning since it is not 100% correct. |
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verilog2vhdl |
Verilog to VHDL converter- mainly targeted for the Verilog-95 constructs. |
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vhdl2systemc |
Utility to convert VHDL definition of an IP into SystemC. There generated SC will require manual refinement. |
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vhdl2verilog |
Verilog to VHDL converter utility. May need manual fine tuning for the complex VHDL constructs like nested records with user defined data types and multi-dimensional arrays. |
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lib2verilog |
Generate verilog mdoule(s) from the Liberty .lib file. |
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vhdltbgen |
Simple testbench generator utility in VHDL. |
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vlogtbgen |
Simple testbench generator utility in Verilog. |
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