- StandardIEEE 1685-2009, 2014 and 2022
- Packages fromVerilog, SystemVerilog, VHDL
- GeneratesUVM and C register models, RTL, docs
- LicenseFree, no license server
Overview
IP-XACT (IEEE 1685) is the XML standard that describes an IP block in a tool-neutral way: its ports, parameters, bus interfaces, memory maps, registers and bit fields, and how instances connect in a design. Package an IP once and any IP-XACT-aware integration tool can consume it, and the register views for RTL, verification and firmware all come from one source instead of three hand-maintained copies.
EDAUtils provides a free, complete IP-XACT toolset for IEEE 1685-2009, 1685-2014 and 1685-2022. A GUI and a 200+ command Tcl shell build components by reading ports and parameters from Verilog, SystemVerilog or VHDL, map bus interfaces, and capture memory maps, registers and bit fields correct by construction. From that component the tools generate RTL, UVM and C register models, validation reports and documentation. See the IP-XACT tools guide for the full command list.
Install and run
This sequence was run against the current release; the output of the first command is a valid IEEE 1685-2009 component.
$ curl -fsSL https://edautils.com/install.sh | sh -s -- baya-shell
$ source $EDAUTILS_ROOT/setup_env.sh
$ verilog2ipxact -in dma.v -top dma -out dma.xml # IEEE 1685-2009 (default)
$ verilog2ipxact -in dma.v -top dma -out dma.xml -v2014 # IEEE 1685-2014
$ verilog2ipxact -in dma.v -top dma -out dma.xml -v2022 # IEEE 1685-2022
$ validateipxact -in dma.xml
$ genregisteruvmmodel -in dma.xml -out dma_regs_pkg.svUseful verilog2ipxact switches: -f filelist for multiple files, -vlnv edautils.com/lib/Clock/1.0 to set the VLNV, -design to emit an IP-XACT design, +incdir+ and +define+ for preprocessing, -search_path to locate referenced components. Linux and Windows, Java 8 or newer, no license server.
The tool chain
Supported standards
| Standard | Versions | Notes |
|---|---|---|
| IP-XACT | IEEE 1685-2009, 1685-2014, 1685-2022 | 1685-2009 is the default output; -v2014 and -v2022 select the newer schemas. SPIRIT 1.4 and 1.5 files are read. |
| Verilog / SystemVerilog | IEEE 1800-2012 grammar; source types 2009, 2012 and 2017 | Used when packaging RTL into a component. |
| VHDL | VHDL-2002 and VHDL-2008 source types | Entities, architectures, packages and generate statements. |
| UPF | IEEE 1801-2013 | Power intent, via upf-shell. |
TGI: the IEEE 1685-2022 generator interface
IP-XACT's Tcl Generator Interface is how a generator script asks the design database questions — give me this component's memory maps, this address block's registers, this field's bit offset — and how it writes a design back. EDAUtils exposes it as a tgi:: Tcl namespace inside ipxact-shell and baya-shell, under the IEEE 1685-2022 call names and argument order, so a generator runs in-process against the design already in memory rather than through a file round trip.
- One implementation, every revision. Components are loaded by
tgi::registerVLNVand answered through a revision-neutral register model, so a 1685-2009, a 1685-2014 and a 1685-2022 component reply to the same calls identically. Designs and components created through TGI are written as 1685-2022 documents. - Older spellings still work. The 2009 and 2014 names —
addComponentInstance,addAdHocConnection,addInterconnection,getFieldBitOffset,getFieldBitWidthand the rest — are aliased onto the 2022 calls, so scripts written against an earlier revision keep running. Only 455 of the 887 names in the 2014 API survive into 2022; the migration scanner reports which of the calls in a given generator are affected before you port it. - Build as well as query.
tgi::createComponent,addComponentWirePort,addVector,createDesign,addDesignComponentInstance,addDesignInterconnection,addDesignAdHocConnection, part selects, tied values and configurable element values — a whole SoC can be assembled through TGI alone. - Proved on real SoCs. Two reference RISC-V SoCs were rebuilt from their IP-XACT purely through TGI and compared node for node against their reference top level: 202 and 588 nodes equal.
Register and memory-map generation
One IP-XACT source of truth, and every consumer generated from it. The RTL, the UVM register abstraction layer, the firmware header and the documentation cannot drift from each other because none of them is hand-maintained.
| Output | Tool | Notes |
|---|---|---|
| Register block RTL | ipxactreg2verilog | Synthesizable register block from the memory map. |
| UVM register model (RAL) | genregisteruvmmodel | Address blocks, parallel and nested banks, register files and fields. -gentests emits a test suite against the generated model. |
| C model for firmware | genregistercmodel | Builds clean under -Wall -Werror for the host and for rv32i/ilp32 cross-compilation. Address subspaces and banks nested inside banks are handled. |
| RALF | genregisteruvmmodel | RALF output, drivable from Tcl. |
| Register documentation | genregisterdochtml, gendocipxact | HTML register documentation and a design document from the component. |
| Spreadsheet round trip | ipxactreg2xlsreg, xls2ipxact | Registers out to a spreadsheet and back. |
| TLM model | ipxact2tlm | SystemC TLM model from the component's memory map. |
Register models are generated for a whole SoC, not just one IP: the UVM RAL and the C model for every register IP in a design are built in one pass, driven through TGI, with the generated UVM compiled and simulated and the generated C compiled for both host and target as part of the release gate.
Recent additions
September 2026
- The
tgi::namespace inipxact-shellandbaya-shell, with 2009/2014 aliases and a migration scanner for existing generator scripts. - Complete-SoC register and memory models — UVM RAL and C for every register IP in a design, built through TGI and gated by compilation and simulation of the generated code.
- Banks in depth — parallel banks, banks nested inside banks, and C address subspaces, in both the UVM and the C generators.
- IEEE 1685-2022 throughout — components, designs and register views created and written at the 2022 revision, with 2009 and 2014 read and upgraded by
upgradeipxact. - Bus interfaces connected across revisions — a 2009 component and a 2022 component connect through their bus interfaces in the same design.
- Design maturity reporting — percentage of unconnected ports, reported from the data model.
- SystemC emitter rebuilt —
verilog2systemc,vhdl2systemcandipxact2tlmoutput audited end to end and building clean as C++.
EDAUtils IP-XACT Offerings
EDAUtils provides complete IP-XACT solutions for design organizations dealing with IP creation or integration. Our intuitive GUI builds IP-XACT Component definitions by reading ports and parameters from RTL, instantiating bus interfaces, intuitively mapping ports/parameters, and defining memories, registers, and bit fields - resulting in correct by construction specifications. All GUI actions generate equivalent Tcl commands for batch mode reuse.
Demo & Tutorials
Capabilities by Domain
| IP-XACT Domain | Capabilities and Features | EDAUtils Tools |
|---|---|---|
| Component |
|
IP-XACT GUI, ipxact-shell, verilog2ipxact, vhdl2ipxact, ipxact2vhdlentity, ipxact2verilog, validateipxact, gendocipxact, ipxactcoherencychecker |
| Registers & Memories |
|
IP-XACT GUI, ipxact-shell, genregisteruvmmodel, genregistercmodel, validateipxact, ipxact2tcl, xls2ipxact |
| Design |
|
verilog2ipxact, ipxact2verilog, ipxact-shell |
Frequently asked questions
tgi:: tcl namespace with the older call names aliased, and spans the whole lifecycle: packaging from Verilog, SystemVerilog and VHDL; bus interface mapping; memory map, register and field capture; generation of RTL, whole-SoC UVM register models, C firmware models, RALF, TLM models and documentation; revision upgrade; schema validation; and coherency checking of the IP-XACT against the RTL it claims to describe. Everything is scriptable headless, so AI agents and CI jobs can drive it end to end, and source code is available on demand.tgi:: namespace inside ipxact-shell and baya-shell, under the standard call names and argument order, so a generator runs in-process against the design already in memory. Components of any revision are loaded by tgi::registerVLNV and answered through a revision-neutral model, so 2009, 2014 and 2022 components reply identically. Only 455 of the 887 names in the 2014 API survive into 2022, so a migration scanner reports which calls in an existing generator are affected before it is ported.-v2014 and -v2022 select the newer schemas, and upgradeipxact converts between revisions.genregisteruvmmodel and genregistercmodel generate the UVM register abstraction layer and the C firmware model for every register IP in a design in one pass, including parallel banks, banks nested inside banks and C address subspaces. -gentests emits a test suite against the generated UVM model. The release gate compiles and simulates the generated UVM and compiles the generated C for both host and rv32i/ilp32 targets.curl -fsSL https://edautils.com/install.sh | sh -s -- ipxact-shell, discovers switches with ipxact-shell -help, and runs a whole flow from one Tcl script.Miscellaneous IP-XACT Utilities
- ipxact2verilog - Generate Verilog module from IP-XACT definition
- ipxact2vhdlentity - Generate VHDL entity from IP-XACT Component
- verilog2ipxact - Generate IP-XACT from Verilog modules
- vhdl2ipxact - Generate IP-XACT from VHDL source
- ipxactcoherencychecker - Validate IP-XACT with Verilog/VHDL implementation
- validateipxact - Syntax and semantic validator
- compareipxact - Logical comparison of two IP-XACT files
- gendocipxact - Generate Word document from IP-XACT
- ipxact2tlm - Generate TLM from IP-XACT Register Definitions
- ipxactinterface2svinterface - Generate SystemVerilog Interface from IP-XACT
- ipxactreg2xlsreg - Generate XLS from IP-XACT for register management
- xls2ipxact - Generate IP-XACT from XLS file
- ipxact2tcl - Generate Tcl commands from existing IP-XACT
- ipxact-shell - Comprehensive Tcl shell for all IP-XACT capabilities
IP-XACT Converters
Import existing RTL straight into IP-XACT.