What IP-XACT tools does EDAUtils provide?

A GUI and Tcl shell (ipxact-shell) for IEEE 1685 component packaging, verilog2ipxact and vhdl2ipxact importers, ipxact2verilog and ipxact2vhdlentity generators, xls2ipxact for registers, genregisteruvmmodel and genregistercmodel, validateipxact, ipxactcoherencychecker and gendocipxact. All free.

Which IP-XACT versions are supported?

IEEE 1685-2009, 1685-2014 and 1685-2022; SPIRIT 1.4 and 1.5 files are read. Output defaults to 1685-2009; pass -v2014 or -v2022 for the newer schemas.

Can I generate IP-XACT from Verilog or VHDL?

Yes. verilog2ipxact -in top.v -top top -out top.xml generates an IP-XACT component with ports, parameters and bus interfaces from Verilog; vhdl2ipxact does the same from VHDL.

Can I generate a UVM register model from IP-XACT?

Yes. genregisteruvmmodel produces a UVM RAL package from the memory maps, registers and fields in an IP-XACT component; genregistercmodel produces the matching C header.

How do I install the EDAUtils IP-XACT tools?

Run: curl -fsSL https://edautils.com/install.sh | sh -s -- ipxact-shell. Or download the archive from edautilsonline.com, extract it and add bin to PATH. Java 8 or newer is required.

IP-XACT Tools - IEEE 1685 Packaging & Registers

StandardIEEE 1685-2009, 2014 and 2022
Packages fromVerilog, SystemVerilog, VHDL
GeneratesUVM and C register models, RTL, docs
LicenseFree, no license server

Overview

IP-XACT (IEEE 1685) is the XML standard that describes an IP block in a tool-neutral way: its ports, parameters, bus interfaces, memory maps, registers and bit fields, and how instances connect in a design. Package an IP once and any IP-XACT-aware integration tool can consume it, and the register views for RTL, verification and firmware all come from one source instead of three hand-maintained copies.

EDAUtils provides a free, complete IP-XACT toolset for IEEE 1685-2009, 1685-2014 and 1685-2022. A GUI and a 200+ command Tcl shell build components by reading ports and parameters from Verilog, SystemVerilog or VHDL, map bus interfaces, and capture memory maps, registers and bit fields correct by construction. From that component the tools generate RTL, UVM and C register models, validation reports and documentation. See the IP-XACT tools guide for the full command list.

Install and run

This sequence was run against the current release; the output of the first command is a valid IEEE 1685-2009 component.

$ curl -fsSL https://edautils.com/install.sh | sh -s -- baya-shell
$ source $EDAUTILS_ROOT/setup_env.sh

$ verilog2ipxact -in dma.v -top dma -out dma.xml            # IEEE 1685-2009 (default)
$ verilog2ipxact -in dma.v -top dma -out dma.xml -v2014     # IEEE 1685-2014
$ verilog2ipxact -in dma.v -top dma -out dma.xml -v2022     # IEEE 1685-2022

$ validateipxact -in dma.xml
$ genregisteruvmmodel -in dma.xml -out dma_regs_pkg.sv

Useful verilog2ipxact switches: -f filelist for multiple files, -vlnv edautils.com/lib/Clock/1.0 to set the VLNV, -design to emit an IP-XACT design, +incdir+ and +define+ for preprocessing, -search_path to locate referenced components. Linux and Windows, Java 8 or newer, no license server.

IP-XACT flow: RTL is read into a component, ports and a bus interface are captured, registers are defined, then IP-XACT XML, a UVM register model, a C header and documentation are generated — Package once from RTL, then generate the IP-XACT component, a UVM register model, a C header and documentation from that single source.

The tool chain

The EDAUtils IP-XACT flow: components, bus interfaces, memory maps and registers.

Supported standards

Standard	Versions	Notes
IP-XACT	IEEE 1685-2009, 1685-2014, 1685-2022	1685-2009 is the default output; `-v2014` and `-v2022` select the newer schemas. SPIRIT 1.4 and 1.5 files are read.
Verilog / SystemVerilog	IEEE 1800-2012 grammar; source types 2009, 2012 and 2017	Used when packaging RTL into a component.
VHDL	VHDL-2002 and VHDL-2008 source types	Entities, architectures, packages and generate statements.
UPF	IEEE 1801-2013	Power intent, via `upf-shell`.

EDAUtils IP-XACT Offerings

EDAUtils provides complete IP-XACT solutions for design organizations dealing with IP creation or integration. Our intuitive GUI builds IP-XACT Component definitions by reading ports and parameters from RTL, instantiating bus interfaces, intuitively mapping ports/parameters, and defining memories, registers, and bit fields - resulting in correct by construction specifications. All GUI actions generate equivalent Tcl commands for batch mode reuse.

Demo & Tutorials

📹 Get Started in Linux

📹 Get Started in Windows

📹 IP-XACT With GUI

📹 IP-XACT in Tcl Shell

Capabilities by Domain

IP-XACT Domain	Capabilities and Features	EDAUtils Tools
Component	Smart GUI to capture VLNV, ports and parameters Import from Verilog and VHDL GUI for bus interfaces with logical to physical port mappings Tcl shell commands for commandline users Coherency checker between RTL and IP-XACT Equivalence checker between revisions IP-XACT Validator and Document Generator	IP-XACT GUI, ipxact-shell, verilog2ipxact, vhdl2ipxact, ipxact2vhdlentity, ipxact2verilog, validateipxact, gendocipxact, ipxactcoherencychecker
Registers & Memories	Single-sourced GUI for Address Block and Memory Map Correct by construct Register, Alternate Register, and Bit Field capture UVM Model generator C Model generator Excel/CSV to IP-XACT Address Block Generator	IP-XACT GUI, ipxact-shell, genregisteruvmmodel, genregistercmodel, validateipxact, ipxact2tcl, xls2ipxact
Design	Create Design from Verilog Instantiate Components Insert interface connections Insert adhoc port-to-port connections Associate Memory Maps with instances Generate Verilog from IP-XACT Design	verilog2ipxact, ipxact2verilog, ipxact-shell

Miscellaneous IP-XACT Utilities

ipxact2verilog - Generate Verilog module from IP-XACT definition
ipxact2vhdlentity - Generate VHDL entity from IP-XACT Component
verilog2ipxact - Generate IP-XACT from Verilog modules
vhdl2ipxact - Generate IP-XACT from VHDL source
ipxactcoherencychecker - Validate IP-XACT with Verilog/VHDL implementation
validateipxact - Syntax and semantic validator
compareipxact - Logical comparison of two IP-XACT files
gendocipxact - Generate Word document from IP-XACT
ipxact2tlm - Generate TLM from IP-XACT Register Definitions
ipxactinterface2svinterface - Generate SystemVerilog Interface from IP-XACT
ipxactreg2xlsreg - Generate XLS from IP-XACT for register management
xls2ipxact - Generate IP-XACT from XLS file
ipxact2tcl - Generate Tcl commands from existing IP-XACT
ipxact-shell - Comprehensive Tcl shell for all IP-XACT capabilities

Download IP-XACT Tools →

IP-XACT Converters

Import existing RTL straight into IP-XACT.

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EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.

Jamil KhatibOpenTech Package

The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.

Jerry FrenkilVP of Engineering, NanoWatt Design

We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.

Dustin PetersonUniversity of Tübingen

I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.

Amal KhailtashLead FPGA Designer, Ciena Communications

The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.

Gene Y. WuUniversity of Texas

We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.

Lucas TeixeiraSMDH

That really helped me now. I got the job done at the right time.

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