200K+ tool usages 50K+ downloads 38 tools, all free Intel Qualcomm Mediatek LG NVIDIA Samsung Broadcom NXP Huawei Texas Instruments AMD ARM Renesas Ciena 40+ more leading semiconductor companies Free for commercial and academic use 200K+ tool usages 50K+ downloads 38 tools, all free Intel Qualcomm Mediatek LG NVIDIA Samsung Broadcom NXP Huawei Texas Instruments AMD ARM Renesas Ciena 40+ more leading semiconductor companies Free for commercial and academic use

Professional SoC Integration & IP-XACT Tools

AI-enabled automation platform reducing RTL generation effort by 10x while eliminating human error in IP integration and hierarchy manipulation

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Three Powerful Solutions

Professional EDA tools and utilities built for modern SoC design workflows

Baya - SoC integration platform

Baya - SoC Integration Platform

AI-Enabled SoC Integration with IP-XACT & Tcl API

Developed in collaboration with semiconductor companies servicing the consumer market. AI-enabled automation reduces RTL generation effort for FPGA, subsystem, or SoC platform and derivative designs by more than an order of magnitude. Supports 12+ bus protocols including AXI4, PCIe, DDR/LPDDR, AHB, APB, USB, Ethernet, and more.

  • 200+ high-level Tcl commands
  • GUI with toolboxes and connection wizard
  • rule-based auto-connections
  • hierarchy manipulation
  • IP-XACT coherency checker
  • multi-methodology integration (XLS/CSV, Port-to-Port, IP-XACT based)
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EDAUtils IP-XACT solution

IP-XACT Solution

IEEE 1685 IP Packaging & Integration

Complete IP-XACT solution for IP creation and integration. Intuitive GUI to build Component definitions by reading RTL ports/parameters, instantiating bus interfaces, defining memories, registers, and bit fields - all correct by construction.

  • Smart GUI for VLNV and component creation
  • verilog2ipxact/vhdl2ipxact importers
  • UVM and C model generators
  • IP-XACT validators
  • document generators
  • comprehensive Tcl shell with 200+ commands
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EDAUtils RTL utilities

RTL Utilities

Parsers, Translators & Generators

Collection of utilities that transform SoC design quality and efficiency by orders of magnitude. Tools often unavailable from EDA vendors but essential during design cycles.

  • SystemVerilog/VHDL parsers with Java/Tcl/Python APIs
  • verilog2vhdl/vhdl2verilog translators
  • testbench generators
  • hierarchy manipulation (create/remove/flatten)
  • interface comparison tools
  • wrapper generators
  • UPF parser
  • and much more
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Articles & Publications

SoC Integration Utilities

Hierarchy and netlist manipulation that ships with Baya. New to the topic? Read the SoC integration and IP assembly guide.

IP-XACT Converters

Import existing RTL straight into IEEE 1685 IP-XACT. See the full IP-XACT solution and the IP-XACT tools guide.

Parsers, Translators and Generators

Standalone utilities from the RTL utilities collection.

Trusted by design teams worldwide

The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately.
Michael TrocinoIC Design Manager, Coherent Logix
Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.
Claudine RaibautEDA Manager, Texas Instruments
Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. Its flexibility is a key reason we have chosen it for use in our Cloud-based platform.
David FritzCEO, Social Silicon
Kanai produced an excellent tool set, which is very useful for complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by the high quality and ease of use.
Boris V. KuznetsovCEO, SOCC
Thanks a lot for creating DesignPlayer and the huge Java class library behind it. Your strong support makes me confident to explore more details in future.
Rolf KemperManager, Mixed Signal Design, Renesas Electronics Europe
EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.
Jamil KhatibOpenTech Package
The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.
Jerry FrenkilVP of Engineering, NanoWatt Design
We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.
Dustin PetersonUniversity of Tübingen
I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.
Amal KhailtashLead FPGA Designer, Ciena Communications
The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.
Gene Y. WuUniversity of Texas
We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.
Lucas TeixeiraSMDH
That really helped me now. I got the job done at the right time.
S. KrishnanIntel
The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately.
Michael TrocinoIC Design Manager, Coherent Logix
Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.
Claudine RaibautEDA Manager, Texas Instruments
Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. Its flexibility is a key reason we have chosen it for use in our Cloud-based platform.
David FritzCEO, Social Silicon
Kanai produced an excellent tool set, which is very useful for complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by the high quality and ease of use.
Boris V. KuznetsovCEO, SOCC
Thanks a lot for creating DesignPlayer and the huge Java class library behind it. Your strong support makes me confident to explore more details in future.
Rolf KemperManager, Mixed Signal Design, Renesas Electronics Europe
EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.
Jamil KhatibOpenTech Package
The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.
Jerry FrenkilVP of Engineering, NanoWatt Design
We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.
Dustin PetersonUniversity of Tübingen
I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.
Amal KhailtashLead FPGA Designer, Ciena Communications
The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.
Gene Y. WuUniversity of Texas
We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.
Lucas TeixeiraSMDH
That really helped me now. I got the job done at the right time.
S. KrishnanIntel

Read all customer feedback →