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Remove Assignments From Netlist

Strip concurrent assignments from a Verilog netlist

This utility has been implemented in order to remove concurrent assignments from a verilog netlist without modifying the functionality. This has been developed in Java (1.8) in order to make it platform independent and bundled as an executable JAR file which can be directly used from the 'lib' directory in the downloaded tar or ZIP file. Example-

Usage

source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
set PATH="%path%;%EDAUTILS_ROOT%\bin"
removeassignments -in <input vlog files > -top <name-of-module-to-be-flattened> -out <out vhdl file name > [-f <file-containing-list-of-vlog-files>] [+incdir+<include-path1>+<include-path2> [+define+macro1+macro2]
OR
java com.eu.miscedautils.verilogparser.RemoveAssignments -in <input vlog files > -top <name-of-module-to-be-flattened> -out <out vhdl file name > [-f <file-containing-list-of-vlog-files>] [+incdir+<include-path1>+<include-path2> [+define+macro1+macro2]

Go through the examples to get a better understanding of this tool. Send mails to help@edautils.com if you need any assistance.

Go to the installation directory i.e the directory where this README file resides and run the runme.csh script.

Get details by executing it as ' removeassignments -help '

Part of the EDAUtils toolset

  • Baya - AI-enabled SoC integration with IP-XACT and a 200+ command Tcl API
  • IP-XACT 1685 solution - component packaging, registers, memory maps and generators
  • RTL utilities - parsers, translators, testbench and document generators
  • Run online free - try this tool in the browser, no install
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Trusted by design teams worldwide

The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately.
Michael TrocinoIC Design Manager, Coherent Logix
Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.
Claudine RaibautEDA Manager, Texas Instruments
Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. Its flexibility is a key reason we have chosen it for use in our Cloud-based platform.
David FritzCEO, Social Silicon
Kanai produced an excellent tool set, which is very useful for complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by the high quality and ease of use.
Boris V. KuznetsovCEO, SOCC
Thanks a lot for creating DesignPlayer and the huge Java class library behind it. Your strong support makes me confident to explore more details in future.
Rolf KemperManager, Mixed Signal Design, Renesas Electronics Europe
EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.
Jamil KhatibOpenTech Package
The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.
Jerry FrenkilVP of Engineering, NanoWatt Design
We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.
Dustin PetersonUniversity of Tübingen
I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.
Amal KhailtashLead FPGA Designer, Ciena Communications
The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.
Gene Y. WuUniversity of Texas
We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.
Lucas TeixeiraSMDH
That really helped me now. I got the job done at the right time.
S. KrishnanIntel
The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately.
Michael TrocinoIC Design Manager, Coherent Logix
Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.
Claudine RaibautEDA Manager, Texas Instruments
Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. Its flexibility is a key reason we have chosen it for use in our Cloud-based platform.
David FritzCEO, Social Silicon
Kanai produced an excellent tool set, which is very useful for complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by the high quality and ease of use.
Boris V. KuznetsovCEO, SOCC
Thanks a lot for creating DesignPlayer and the huge Java class library behind it. Your strong support makes me confident to explore more details in future.
Rolf KemperManager, Mixed Signal Design, Renesas Electronics Europe
EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.
Jamil KhatibOpenTech Package
The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.
Jerry FrenkilVP of Engineering, NanoWatt Design
We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.
Dustin PetersonUniversity of Tübingen
I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.
Amal KhailtashLead FPGA Designer, Ciena Communications
The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.
Gene Y. WuUniversity of Texas
We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.
Lucas TeixeiraSMDH
That really helped me now. I got the job done at the right time.
S. KrishnanIntel

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