This tool generates Verilog testbench with random stimuli. User can specify clocks and resets with waveforms and optionally associates ports with the same. It also generates ModelSim and NCSim compilation & simulation scripts.

Usage

Download and extract the tar file and follow the simple steps/commands to generate the testbench. There are few examples which can be used as reference. Here is one example--

source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
set PATH="%path%;%EDAUTILS_ROOT%\bin"
gentbvlog -in simple_and.v -top simple_and -out tb.v [+incdir+dir1+dir2] [-clk "clock1@10{data:address}" -clk clk2] [-rst reset1 -rst reset2]
OR
java com.eu.miscedautils.gentbvlog.GenTBVlog -in simple_and.v -top simple_and -out tb.v [+incdir+dir1+dir2] [-clk clock1] [-rst reset1]

Online Video Demo

% gentbvlog -in include_header.v +incdir+include1+include2 -top include_header -out tb.v

Simulation with ModelSim

%vlib work

%vmap work work

%vlog include_header.v +incdir+include1+include2

% vlog tb.v

%vsim -c -lib work testbench < run.do

....

VSIM 1> run -all

# 0 in1 = xx , in2 = xxxxxx , out1 = 00xx

# 5 in1 = 00 , in2 = 100100 , out1 = 0000

# 10 in1 = 10 , in2 = 000001 , out1 = 0000

# 15 in1 = 00 , in2 = 001001 , out1 = 0000

# 20 in1 = 01 , in2 = 100011 , out1 = 0001

# 25 in1 = 00 , in2 = 001101 , out1 = 0000

# 30 in1 = 10 , in2 = 001101 , out1 = 0000

# 35 in1 = 01 , in2 = 100101 , out1 = 0001

.....

# 195 in1 = 00 , in2 = 001101 , out1 = 0000

# ** Note: $finish : tb.v(30)

# Time: 200 ns Iteration: 0 Instance: /testbench

Generated Verilog Testbench: tb.v

//////////////////////////////////////////////////////////////////////////////////////////////////////

// //

// This testbench has been generated by the Verilog //

// testbench generator. //

// Contact help@edautils.com for support/info. //

// //

/////////////////////////////////////////////////////////////////////////////////////////////////////

// Generated by : Ron on 5/23/10 9:10 PM

module testbench;

reg [0:7] indata_array;

wire [3:0] tmp_out1;

include_header inst(.in1(indata_array[0:1]), .in2(indata_array[2:7]), .out1(tmp_out1));

always

begin

#5 indata_array = $random;

end

initial

begin

$monitor($time, " in1 = %b , in2 = %b , out1 = %b ",

indata_array[0:1], indata_array[2:7], tmp_out1);

end

initial

begin

#200 $finish;

end

endmodule

Part of the EDAUtils toolset

Baya - AI-enabled SoC integration with IP-XACT and a 200+ command Tcl API
IP-XACT 1685 solution - component packaging, registers, memory maps and generators
RTL utilities - parsers, translators, testbench and document generators
Run online free - try this tool in the browser, no install

Download Verilog Testbench Generator →

Trusted by design teams worldwide

The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately.

Michael TrocinoIC Design Manager, Coherent Logix

Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.

Claudine RaibautEDA Manager, Texas Instruments

Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. Its flexibility is a key reason we have chosen it for use in our Cloud-based platform.

David FritzCEO, Social Silicon

Kanai produced an excellent tool set, which is very useful for complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by the high quality and ease of use.

Boris V. KuznetsovCEO, SOCC

Thanks a lot for creating DesignPlayer and the huge Java class library behind it. Your strong support makes me confident to explore more details in future.

Rolf KemperManager, Mixed Signal Design, Renesas Electronics Europe

EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.

Jamil KhatibOpenTech Package

The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.

Jerry FrenkilVP of Engineering, NanoWatt Design

We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.

Dustin PetersonUniversity of Tübingen

I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.

Amal KhailtashLead FPGA Designer, Ciena Communications

The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.

Gene Y. WuUniversity of Texas

We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.

Lucas TeixeiraSMDH

That really helped me now. I got the job done at the right time.

S. KrishnanIntel

The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately.

Michael TrocinoIC Design Manager, Coherent Logix

Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.

Claudine RaibautEDA Manager, Texas Instruments

Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. Its flexibility is a key reason we have chosen it for use in our Cloud-based platform.

David FritzCEO, Social Silicon

Kanai produced an excellent tool set, which is very useful for complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by the high quality and ease of use.

Boris V. KuznetsovCEO, SOCC

Thanks a lot for creating DesignPlayer and the huge Java class library behind it. Your strong support makes me confident to explore more details in future.

Rolf KemperManager, Mixed Signal Design, Renesas Electronics Europe

EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.

Jamil KhatibOpenTech Package

The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.

Jerry FrenkilVP of Engineering, NanoWatt Design

We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.

Dustin PetersonUniversity of Tübingen

I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.

Amal KhailtashLead FPGA Designer, Ciena Communications

The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.

Gene Y. WuUniversity of Texas

We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.

Lucas TeixeiraSMDH

That really helped me now. I got the job done at the right time.

S. KrishnanIntel