CAD Reference Flows

What it isFront-end CAD reference flow
DrivesIcarus, VCS, Verilator, Yosys, ANVL
PlatformLinux, prebuilt binaries
LicenseFree, no license server

FECAD is the EDAUtils front-end CAD reference flow. It generates the Makefiles and configuration that drive RTL simulation, static checks, synthesis, equivalence checking and DV regression across a hierarchy of soft IPs, hard IPs, VIPs and SoCs, and it records which test proves which requirement.

FECAD does not replace your EDA tools. It sits above them: you describe the design and its dependencies once, and the flow generates the per-step Makefiles that call the tools you already use.

Download FECAD Flow (Linux binaries) →

FECAD flow: scaffold the IP, generate file lists and makefiles, then run simulation, static checks, synthesis and equivalence checking, ending in summaries and a traceability report — Scaffold once, generate the build, then every flow domain runs from the same configuration.

The design flow

Step	What runs	Generated by
Project and design setup	Flow root, tool versions, IP directory and dependencies	`create_structures`, `generate_ip_dependencies`
Flow configuration	File lists, waivers, constraints	`generate_flat_filelists`, `get_config_value`
RTL generation	Connected RTL from IP metadata	Baya
Compile and elaborate	ANVL (`anvl`, `anvh`)	`generate_misc_makefile`
Simulation	Icarus Verilog, VCS	`generate_sim_makefile`
Static checks and linting	Verilator	`generate_static_check_makefile`
Synthesis	Yosys	`generate_synthesis_makefile`
Equivalence check	Yosys	`generate_eq_check_makefile`
Release	IPQC gate, then RTL release	`report_summary_*`

The DV flow

DV environment and build setup pull in the VIPs and the released RTL, compile to a.out or simv, then run the regression in parallel. Logs are parsed into a summary and a coverage report.

$ generate_dv_makefile
$ dvregress -exe ./simv -model my_model -designconfig DUT_1 \
            -testplan adder_ip/testplan/DUT_1.yml -parse_log

The testplan compiles into the Tests.list format the runner already reads, and the compiled list is written into the regression directory so you can see exactly what ran. -override KEY=VAL beats the testplan value for every row.

Requirement to test traceability

A requirement is only useful if you can say which test proves it. FECAD records that chain in three plain YAML files inside the IP, with no server involved and nothing leaving your network.

<ip>/req/<area>.yml        requirements
<ip>/testreq/<area>.yml    test requirements
<ip>/testplan/<DUT>.yml    testplan rows, one per test

Every entry carries an id that is unique across the IP; testplan rows reference test requirements, which reference requirements. traceability_report walks the chain and reports it. The bundled adder_ip/ is a complete worked example of all three files.

Reporting

report_summary_sim_icarus - simulation pass and fail summary
report_summary_static_checks_verilator - lint and static check summary
report_summary_synthesis_yosys - synthesis results
report_summary_anvl - compile and elaboration results
parse_log - turns raw tool logs into structured results
traceability_report - requirement to test coverage

Install

$ tar xzf fecadflow-<version>.tar.gz
$ cd fecadflow-<version>
$ ./install.sh [install_dir]        # default: ~/fecadflow

The installer checks for Python 3.8 or newer, installs the small set of Python dependencies, copies the bundle into place and writes env/setup/set_path. Every fecadflow command checks for a signed license file, so copy the edautils.lic issued to you into $INSTALL_DIR/edautils.lic.

Run the end-to-end example

$ bash $INSTALL_DIR/examples/run_end_to_end.sh

This scaffolds a small sample IP, a clock divider, with create_structures, then drives it through every flow domain. It takes well under a minute, and the script is the same command sequence you would run by hand for a real IP.

Flow domain	Tool	What it does
`sim`	Icarus Verilog	Compiles the RTL with `iverilog`
`static_checks`	Verilator	Lints the RTL with `--lint-only`
`synthesis`	Yosys	Synthesizes RTL to a gate netlist
`eq_check`	Yosys	Equivalence-checks RTL against the synthesized netlist
`misc`	ANVL	Compile and elaborate; skipped automatically when `anvl` is not installed

Scaffold your own IP

$ cd $EDAUTILS_RTL_PROJECT_ROOT
$ create_structures -techno <techno> -name <your_ip> -full_structure true
$ cd <your_ip>
$ echo 'src/rtl/your_module.v' > filelists/<designconfig>/rtl.f

Then, for each flow domain you need:

$ cd <flow_domain>/<tool>
$ cp $EDAUTILS_FECAD_FLOW_ROOT/defaults/<flow_domain>/<tool>/Makefile .
$ make TECHNO=<techno> TRIAL_NAME=trial TOP_MODULE_NAME=<TOP> \
       DESIGN_CFG_NAME=<designconfig> OUTPUT_DIR=<out> genfilelists
$ make ... genmakefiles
$ make ... <tool>_compile

Run those as three separate make invocations

genmakefiles writes the file that the <tool>_compile target lives in.
make reads its includes once, at parse time, so make t1 t2 t3 in one command cannot see a target that did not exist when it started.
The symptom of getting this wrong is No rule to make target '<tool>_compile'.

Troubleshooting

Symptom	Cause and fix
`Couldn't find valid license`	`edautils.lic` is missing or expired, or `EDAUTILS_LICENSE_FILE` points at the wrong path.
`No rule to make target '<tool>_compile'`	The three make targets were run in one invocation. Run them separately, as above.
eq_check errors on an async-reset flip-flop	Sensitive to the installed Yosys version, not to your design.

Frequently asked questions

What is the FECAD flow?

FECAD is EDAUtils' front-end CAD reference flow. It generates the Makefiles and configuration that drive RTL simulation, static checks, synthesis, equivalence checking and DV regression across a hierarchy of soft IPs, hard IPs, VIPs and SoCs, and records requirement-to-test traceability in plain YAML files.

Which EDA tools does FECAD drive?

Icarus Verilog and VCS for simulation, Verilator for static checks and linting, Yosys for synthesis and equivalence checking, and ANVL (anvl/anvh) for compile and elaboration. The flow generates Makefiles for each step rather than replacing the tools.

How does requirement traceability work?

Three YAML files inside each IP: req/<area>.yml for requirements, testreq/<area>.yml for test requirements, and testplan/<DUT>.yml for testplan rows. Every entry carries a unique id, and testplan rows reference test requirements which reference requirements. Nothing reaches the network.

How do I run a regression?

dvregress -exe <path/to/simv> -model <model> -designconfig DUT_1 -testplan <ip>/testplan/DUT_1.yml -parse_log. The testplan compiles into the Tests.list format the runner already reads, written into the regression directory so you can see exactly what ran.

Is the FECAD source available?

Prebuilt Linux binaries are available for download. The Python source bundle is not distributed at this time.

What does FECAD cost?

Nothing. Like every EDAUtils tool it is free for commercial and academic use, with no license server.

Download FECAD Flow →