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Verilog Flattener

Flatten instances or an entire Verilog design into a single module

If you have any question concerning bug fixes, new features and enhancements, please don't hesitate to contact. You will get the best solutions at the earliest.

This utility takes list of verilog RTL files and the top verilog module name as input and removes all the instances by pulling that's functionality in the top module. You may also consider to explore the flatteninstances tool to flatten specific hierarchical instances. This has been developed in Java (1.8) in order to make it platform independent.

Usage

source setup_env ( 'sh' or 'csh' for Unix and '.bat' for Windows DOS Shell )
Alternatively, for Unix
setenv EDAUTILS_ROOT /LinuxShare/WinDataFiles/ProjectRoot/temp/DesignPlayer-linux.x86/01MAY2014
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014
set PATH="%path%;%EDAUTILS_ROOT%\bin"
flatteverilog -in foo.v -top mytop -out flattened.v -hier_delim .
OR
java com.eu.miscedautils.verilogparser.FlattenVerilog -in foo.v -top mytop -out flattened.v -hier_delim .

Where the '.' is the hierarchy delimiter.

Get details of available options by executing it as ' flattenverilog -help '

Options are as below:

-in <input vlog file> : Mandatory, input verilog file

-top <name-of-module-to-be-flattened> : Mandatory, top module name

-out <output file name > : Optional, output file name

-disble_assgn_merge : Optional, disables assignment merging

-elaborate : Optional, elaborates design

-f <file-containing-list-of-vlog-files> : List of verilog input files

-hier_delim <hierarchy-delimiter-character> : Optional, hierarchy delimiter char, default is '_'

+incdir+<include-path1>+<include-path2> : Optional, compiler directives

-flatten_undefined_modules : Optional, enables flattening of undefined modules as well

-stop_at_leaf : Optional, disables flattening of leaf module instances

-no_hier : Optional, disables flattening of hierarchies

-remove_unused_nets : Optional, removes unused nets

-rename_nets : Optional, renames nets to shorter net names

Similar tool ungroup/flatteninstances

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Part of the EDAUtils toolset

  • Baya - AI-enabled SoC integration with IP-XACT and a 200+ command Tcl API
  • IP-XACT 1685 solution - component packaging, registers, memory maps and generators
  • RTL utilities - parsers, translators, testbench and document generators
  • Run online free - try this tool in the browser, no install
Download Verilog Flattener →

Trusted by design teams worldwide

The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately.
Michael TrocinoIC Design Manager, Coherent Logix
Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.
Claudine RaibautEDA Manager, Texas Instruments
Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. Its flexibility is a key reason we have chosen it for use in our Cloud-based platform.
David FritzCEO, Social Silicon
Kanai produced an excellent tool set, which is very useful for complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by the high quality and ease of use.
Boris V. KuznetsovCEO, SOCC
Thanks a lot for creating DesignPlayer and the huge Java class library behind it. Your strong support makes me confident to explore more details in future.
Rolf KemperManager, Mixed Signal Design, Renesas Electronics Europe
EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.
Jamil KhatibOpenTech Package
The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.
Jerry FrenkilVP of Engineering, NanoWatt Design
We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.
Dustin PetersonUniversity of Tübingen
I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.
Amal KhailtashLead FPGA Designer, Ciena Communications
The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.
Gene Y. WuUniversity of Texas
We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.
Lucas TeixeiraSMDH
That really helped me now. I got the job done at the right time.
S. KrishnanIntel
The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately.
Michael TrocinoIC Design Manager, Coherent Logix
Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.
Claudine RaibautEDA Manager, Texas Instruments
Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. Its flexibility is a key reason we have chosen it for use in our Cloud-based platform.
David FritzCEO, Social Silicon
Kanai produced an excellent tool set, which is very useful for complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by the high quality and ease of use.
Boris V. KuznetsovCEO, SOCC
Thanks a lot for creating DesignPlayer and the huge Java class library behind it. Your strong support makes me confident to explore more details in future.
Rolf KemperManager, Mixed Signal Design, Renesas Electronics Europe
EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.
Jamil KhatibOpenTech Package
The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.
Jerry FrenkilVP of Engineering, NanoWatt Design
We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.
Dustin PetersonUniversity of Tübingen
I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.
Amal KhailtashLead FPGA Designer, Ciena Communications
The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.
Gene Y. WuUniversity of Texas
We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.
Lucas TeixeiraSMDH
That really helped me now. I got the job done at the right time.
S. KrishnanIntel

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