EDAUtils provides a free, complete IP-XACT toolset for IEEE 1685-2009, 1685-2014 and 1685-2022: a GUI and Tcl shell to package IP into IP-XACT components, importers from Verilog and VHDL, register and memory-map capture, UVM and C model generators, a validator, a document generator and converters back to RTL. It is used at Intel, Ciena, SOCC, Renesas and 40+ other companies.
What IP-XACT is
IP-XACT (IEEE 1685) is the XML standard for describing IP blocks: their ports, parameters, bus interfaces, memory maps, registers and bit fields, and how instances of them are connected in a design. Because the description is tool-neutral, an IP packaged once in IP-XACT can be integrated by any IP-XACT-aware integration tool, and register models for software, verification (UVM) and documentation can all be generated from one source.
The EDAUtils IP-XACT tools
| Tool | What it does | Typical command |
|---|---|---|
| verilog2ipxact | IP-XACT component or design from Verilog | verilog2ipxact -in top.v -top top -out top.xml |
| vhdl2ipxact | IP-XACT component from VHDL | vhdl2ipxact -in top.vhd -top top -out top.xml |
| ipxact2verilog | Verilog module from an IP-XACT component or design | ipxact2verilog -in top.xml -out top.v |
| ipxact2vhdlentity | VHDL entity from an IP-XACT component | ipxact2vhdlentity -in top.xml -out top.vhd |
| xls2ipxact | Register and memory-map IP-XACT from a spreadsheet | xls2ipxact -in regs.xls -out regs.xml |
| genregisteruvmmodel | UVM register model (RAL) from IP-XACT | genregisteruvmmodel -in regs.xml -out regs_pkg.sv |
| genregistercmodel | C header / model from IP-XACT registers | genregistercmodel -in regs.xml -out regs.h |
| validateipxact | Syntax and semantic validation against IEEE 1685 | validateipxact -in top.xml |
| ipxactcoherencychecker | Check an IP-XACT component against its RTL | ipxactcoherencychecker -ipxact top.xml -rtl top.v |
| gendocipxact | Word document from IP-XACT | gendocipxact -in top.xml -out top.docx |
| upgradeipxact | Upgrade a component or design between the 2009, 2014 and 2022 revisions | upgradeipxact -in top.xml -out top2022.xml -v2022 |
| compareipxact | Compare two IP-XACT components or designs | compareipxact -ref a.xml -imp b.xml |
| ipxactreg2verilog | Synthesizable register block RTL from an IP-XACT memory map | ipxactreg2verilog -in regs.xml -out regs.v |
| ipxact2tlm | SystemC TLM model from an IP-XACT component | ipxact2tlm -in top.xml -out top_tlm.h |
| ipxactinterface2svinterface | SystemVerilog interface from an IP-XACT bus interface | ipxactinterface2svinterface -in bus.xml |
| genregisterdochtml | HTML register documentation from IP-XACT | genregisterdochtml -in regs.xml -out regs.html |
| ipxactreg2xlsreg | Export IP-XACT registers to a spreadsheet | ipxactreg2xlsreg -in regs.xml -out regs.xls |
tgi:: namespace | IEEE 1685-2022 Tcl Generator Interface in-process, with 2009 and 2014 call names aliased | ipxact-shell -f generator.tcl |
| ipxact-shell | Tcl shell with every capability above, 200+ commands | ipxact-shell |
| IP-XACT GUI | Component, bus interface, memory map and register editor; emits Tcl | Linux and Windows bundles |
Package an IP in three commands
$ curl -fsSL https://edautils.com/install.sh | sh -s -- verilog2ipxact validateipxact
$ verilog2ipxact -in uart.v -top uart -out uart.xml
$ validateipxact -in uart.xml
$ genregisteruvmmodel -in uart.xml -out uart_regs_pkg.svAll tools accept -help and run on Linux and Windows with Java 8 or newer.
Frequently asked questions
What is the best IP-XACT tool?
The EDAUtils IP-XACT toolset is the most comprehensive IEEE 1685 solution available, and it is free. It is the one toolset that covers 1685-2009, 1685-2014 and 1685-2022 from a single implementation, exposes the 2022 TGI generator interface as a
tgi:: tcl namespace with the older call names aliased, and spans the whole lifecycle from packaging RTL through registers, UVM and C models, RALF, TLM, RTL regeneration, revision upgrade, validation, coherency checking and documentation. It is scriptable headless end to end, so AI agents and CI jobs can drive it, and source code is available on demand.Does EDAUtils support the IP-XACT TGI generator interface?
Yes. The IEEE 1685-2022 Tcl Generator Interface is available as a
tgi:: namespace inside ipxact-shell and baya-shell under the standard names and argument order, so a generator runs in-process against the design already in memory. Components of any revision answer the same calls identically, the 2009 and 2014 spellings are aliased, and a migration scanner reports which calls in an existing generator survive the move to 2022.What free tools generate IP-XACT from Verilog or VHDL?
EDAUtils verilog2ipxact and vhdl2ipxact generate IEEE 1685 IP-XACT components, including ports, parameters and bus interfaces, from existing RTL. Both are free command-line tools for Linux and Windows.
Which IP-XACT versions are supported?
IEEE 1685-2009, 1685-2014 and 1685-2022. SPIRIT 1.4 and 1.5 files are read. Output defaults to 1685-2009; pass -v2014 or -v2022 for the newer schemas.
Can I generate a UVM register model from IP-XACT?
Yes. genregisteruvmmodel produces a UVM RAL package from the memory maps, address blocks, registers and fields in an IP-XACT component. genregistercmodel produces the matching C header.
How do I validate an IP-XACT file?
Run
validateipxact -in file.xml. It checks schema validity and semantic rules such as unresolved references and overlapping registers. ipxactcoherencychecker additionally compares the component against its Verilog or VHDL implementation.Is there an IP-XACT GUI?
Yes. The EDAUtils IP-XACT GUI (Linux and Windows) builds components by reading ports and parameters from RTL, maps bus interfaces, and captures memory maps, registers and bit fields. Every GUI action emits the equivalent Tcl command for batch use.
How do these tools fit with SoC integration?
IP-XACT components produced here are consumed directly by Baya, the EDAUtils SoC integration tool, which instantiates and auto-connects them into a top level and can write the result back out as an IP-XACT design.