This utility has been developed for those who want to convert an existing verilog design into VHDL. The generated VHDL may not work as is and may require minor manual correction in order to ensure the VHDL data type matching. This has been developed in Java (1.8) in order to make it platform independent and bundled as an executable JAR file.
Usage
source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
set PATH="%path%;%EDAUTILS_ROOT%\bin"
verilog2vhdl -in simple_and.v -top simple_and_top -out simple_and.vhd
OR
java com.eu.miscedautils.verilog2vhdl.verilog2vhdl -in simple_and.v -top simple_and -out output.vhdYou can provide multiple Verilog files even with wildcard like *.v through the -filelist switch. You can use the -sort switch to tell the tool to sort the files before processing them, this -sort switch is mandatory if your input files are in random order. Also, you can exclude files with the -excludefilelist switch which also supports wildcards .
There are other switches like -only_entity to create just the entity corresponding to the specified top. Similarly, there is -only_component to create a component declaration corresponding to the specified module.
This output VHDL file is dependent on the following two files which are part of this tool's tar ball-
$EDAUTILS_ROOT/vhdl_pkgs/src/misc/misc.vhd
$EDAUTILS_ROOT/vhdl_pkgs/src/misc/vl2vh_primitives.vhd
This is how you can compile and simulate the generated VHDL the modelsim simulator-
vlib misc
vlib vl2vh_work
vmap misc misc
vmap vl2vh_work vl2vh_work
vcom -work misc $EDAUTILS_ROOT/vhdl_pkgs/src/misc/misc.vhd
vcom -work misc
$EDAUTILS_ROOT/vhdl_pkgs/src/misc/vl2vh_primitives.vhd
vcom -work vl2vh_work simple_and.vhd
vsim -c -lib vl2vh_work simple_and_top
Get details by executing it as ' verilog2vhdl -help '
Send your feedback to help@edautils.com for further improvement of this tool.
Known Limitations:
1) This tools assumes that the parameters are of INTEGER type and not of type string. It blindly defines those as integer and initializes the same by converting the verilog values into INTEGER. It may require manual intervention to rectify this.
2) The expressions type in the 'IF' condition, '=' and '/=' operator, assignment will require intervention since VHDL is strongly typed.
3) Some verilog predefined primitives are not supported, e.g. transif0, transif1, trans .
4) System Verilog is not supported. Only limited construct in Verilog-2K is supported
Relevant files
vl2vh_primitives.vhd
misc.vhd
cells.vhd
See Also vhdl2verilog
Watch Online Demo
Part of the EDAUtils toolset
- Baya - AI-enabled SoC integration with IP-XACT and a 200+ command Tcl API
- IP-XACT 1685 solution - component packaging, registers, memory maps and generators
- RTL utilities - parsers, translators, testbench and document generators
- Run online free - try this tool in the browser, no install