200K+ tool usages50K+ downloads38 tools, all freeIntelQualcommMediatekLGNVIDIASamsungBroadcomNXPHuaweiTexas InstrumentsAMDARMRenesasCiena40+ more leading semiconductor companiesFree for commercial and academic use200K+ tool usages50K+ downloads38 tools, all freeIntelQualcommMediatekLGNVIDIASamsungBroadcomNXPHuaweiTexas InstrumentsAMDARMRenesasCiena40+ more leading semiconductor companiesFree for commercial and academic use
About EDAUtils
Free SoC integration and IP-XACT tools, built in Bangalore since 2012
EDAUtils is an initiative born out of a passion that its founder has been following for close to two decades. Kanai Ghosh started his career in 1998 and has spent close to three decades in EDA tool and CAD flow and methodology development, deployment and support, with professional exposure across NXP, Intel, Qualcomm, Texas Instruments, Interra and Delsoft.
After a number of years working in EDA and CAD tool development he set out to design his own suite of tools, building it nights and weekends in and around his day job. edautils.com went live in January 2012 from Bangalore, India, and the tools have been free to download from the first day.
The focus was deliberate. Modern SoC projects can include more than 250 pieces of IP, with multiple power and voltage domains that force the designer to change the design on the fly as constraints evolve, trading power, performance and area against the project budget. That integration step is where the manual effort and the errors concentrate, and that is what Baya automates.
How it started
Baya was built on the IEEE 1685-2009 IP-XACT standard, in the founder's words, to take advantage of the IEEE 1685-2009 IP-XACT initiative. From the beginning it shipped in both GUI and Tcl command modes, with a low-level API for manipulating the design database directly and a design-maturity report based on unconnected pins and ports. It had more than 100 Tcl commands then; it has more than 200 now, and reads IP-XACT 1685-2009, 1685-2014 and 1685-2022.
Alongside Baya came Brigid, a set of utilities around VHDL and Verilog that automate many small steps in the design process which previously had to be handled manually. In the founder's description at the time, Brigid included VHDL and Verilog parsers, testbench generators, vhdl2verilog and verilog2vhdl translators, verilog2systemc and vhdl2systemc translators, features for clock and reset tree extraction, a Verilog and VHDL sorting utility, Verilog encryption and decryption support for IP protection, and a design hierarchy and module dependency browser. Those utilities are the RTL utilities collection today.
Both were implemented in Java, a deliberate choice:
It is one of the most quickly evolving programming languages, which is widely used to develop software. Using Java, new applications can be developed quickly and easily without thinking about the memory and pointer issues that come up with C and C++.
Kanai Ghosh, EDACafe IP Showcase, interviewed by Peggy Aycinena
Where it got to
Then
Now
edautils.com launched, January 2012
38 tools, still free, no license server
More than 10,000 downloads in 2012
50K+ downloads, 200K+ recorded tool usages
60,000+ unique visitors in the first years
Users at Intel, Texas Instruments, NVIDIA, Samsung, Broadcom, Qualcomm, Renesas, Ciena and 40+ more
Baya on IP-XACT 1685-2009, 100+ Tcl commands
IP-XACT 1685-2009, 2014 and 2022; 200+ Tcl commands
Brigid: VHDL and Verilog utilities
Parsers, translators, testbench and document generators, UPF and VCD
Desktop downloads only
Run the tools in the browser at edautilsonline.com, plus the FECAD reference flow
In the press
Kanai Ghosh: A singular effort that changes the conversation
Peggy Aycinena · EDACafe, IP Showcase ·
There's a guy working away in Bangalore today who would like to change your ideas about what you pay for EDA tools. His name is Kanai Ghosh and his tool suite is called edautils, as in EDA Utilities. I spoke with Kanai on Skype recently about his efforts.
He told me that after a number of years working in EDA and CAD tool development, he decided to design his own suite of tools. Now several years into that process, working nights and weekends in and around his day job, Kanai's tools are available for free download on his website.
Per Kanai, edautils pays particular attention to problems associated with integrating IP into larger SoC projects, a critical problem, he says, because today's design projects can include more than 250 pieces of IP.
Clearly, Kanai Ghosh has been working hard. If you're worried, however, that he's been spending his nights and weekends developing all of this stuff, but having little or no traction out in the real world, think again. [...] His is the type of effort that changes the conversation about how people develop tools for design, and what they pay for them.
OpenTech Package - included as a featured application
What users say - feedback from Intel, TI, Renesas, Ciena and several universities
Get in touch
Support, bug reports and feature requests go to help@edautils.com, and the founder still answers them. Licensing and commercial questions go to sales@edautils.com.
Kanai Ghosh, an EDA and CAD tool developer based in Bangalore, India. He built the first tools nights and weekends around his day job and launched edautils.com in January 2012.
Why are the EDAUtils tools free?
The tools exist to remove cost as a barrier to good SoC integration tooling. Every tool is free for commercial and academic use, with no license server.
How many people use EDAUtils?
More than 10,000 downloads in 2012 and over 60,000 unique visitors in the first years, growing to 200K+ recorded tool usages and 50K+ downloads at Intel, Texas Instruments, NVIDIA, Samsung, Renesas, Ciena and 40+ other companies.
How do I contact EDAUtils?
Email help@edautils.com for support and sales@edautils.com for licensing and commercial questions. Every tool also prints the support address in its banner.
Trusted by design teams worldwide
The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately.
Michael TrocinoIC Design Manager, Coherent Logix
Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.
Claudine RaibautEDA Manager, Texas Instruments
Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. Its flexibility is a key reason we have chosen it for use in our Cloud-based platform.
David FritzCEO, Social Silicon
Kanai produced an excellent tool set, which is very useful for complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by the high quality and ease of use.
Boris V. KuznetsovCEO, SOCC
Thanks a lot for creating DesignPlayer and the huge Java class library behind it. Your strong support makes me confident to explore more details in future.
Rolf KemperManager, Mixed Signal Design, Renesas Electronics Europe
EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.
Jamil KhatibOpenTech Package
The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.
Jerry FrenkilVP of Engineering, NanoWatt Design
We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.
Dustin PetersonUniversity of Tübingen
I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.
Amal KhailtashLead FPGA Designer, Ciena Communications
The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.
Gene Y. WuUniversity of Texas
We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.
Lucas TeixeiraSMDH
That really helped me now. I got the job done at the right time.
S. KrishnanIntel
The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately.
Michael TrocinoIC Design Manager, Coherent Logix
Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.
Claudine RaibautEDA Manager, Texas Instruments
Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. Its flexibility is a key reason we have chosen it for use in our Cloud-based platform.
David FritzCEO, Social Silicon
Kanai produced an excellent tool set, which is very useful for complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by the high quality and ease of use.
Boris V. KuznetsovCEO, SOCC
Thanks a lot for creating DesignPlayer and the huge Java class library behind it. Your strong support makes me confident to explore more details in future.
Rolf KemperManager, Mixed Signal Design, Renesas Electronics Europe
EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.
Jamil KhatibOpenTech Package
The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.
Jerry FrenkilVP of Engineering, NanoWatt Design
We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.
Dustin PetersonUniversity of Tübingen
I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.
Amal KhailtashLead FPGA Designer, Ciena Communications
The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.
Gene Y. WuUniversity of Texas
We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.
Lucas TeixeiraSMDH
That really helped me now. I got the job done at the right time.
