VHDL Testbench Generator

This utility has been developed primarily for those who are learning VHDL and want to do a quick validation of their design(s). However, this tool can also be used for design/DV purpose. One such occasion could be when the RTL owner needs to compile, elaborate and run the 0th time simulation. The 0th time simulation is required in order to ensure that the simulation bringup is correct. There are certain design issues which does not show up until the design gets simulated at the 0th time.

You need Java JRE 1.8 or above to use all these utilities.

Usage

Download and extract the tar file and follow the simple steps/commands to generate the testbench. There are few examples which can be used as reference. Here is one example-

source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
set PATH="%path%;%EDAUTILS_ROOT%\bin"
gentbvhdl -in simple_bittype.vhd -top simple_bittype -out tb.vhd [-clk "clock1@10{data:address}" -clk clk2] [-rst reset1 -rst reset2]
OR
java com.eu.miscedautils.gentbvhdl.GenerateVHDLTestBench -in simple_bittype.vhd -top simple_bittype -out tb.vhd [-clk "clock1@10{data:address}" -clk clk2] [-rst reset1 -rst reset2]

Limitation

This tool fails to create the test vectors if the top module ports or generics contains user defined data types. It only supports predefined STD and IEEE data types.

You may consider to convert the VHDL into Verilog using vhdl2verilog and then generate a Verilog testbench generator using the verilog testbench generator tool .

Commands to simulate this testbench with Modelsim simulator

%vlib work

%vmap work work

%vcom ieee_std_logic_vector.vhd tb.vhd

%vsim -c -lib work tb_ieee_std_logic_vector_tb

VSIM 1> run 100ns

# Time = 0 ns in1 = UUUU in2 = UUUU out1 = UUUU

# Time = 0 ns in1 = 1111 in2 = 1110 out1 = UUUU

# Time = 0 ns in1 = 1111 in2 = 1110 out1 = 1110

# Time = 5 ns in1 = 1111 in2 = 1000 out1 = 1110

# Time = 5 ns in1 = 1111 in2 = 1000 out1 = 1000

# Time = 10 ns in1 = 1010 in2 = 0101 out1 = 1000

# Time = 10 ns in1 = 1010 in2 = 0101 out1 = 0000

...

...

# Time = 100 ns in1 = 1111 in2 = 0100 out1 = 0100

VSIM 2> quit

Generated Testbench: tb.vhd

library ieee;

use ieee.numeric_std.all;

use ieee.std_logic_1164.all;

package tb_conv_pack is

....

....

end package tb_conv_pack;

package body tb_conv_pack is

....

....

end package body tb_conv_pack;

library STD;

library ieee;

use std.textio.all;

use ieee.math_real.all; -- for UNIFORM, TRUNC

use ieee.numeric_std.all; -- for TO_UNSIGNED

use ieee.std_logic_1164.all;

use ieee.std_logic_textio.all;

use work.tb_conv_pack.all;

entity tb_ieee_std_logic_vector_tb is

end entity tb_ieee_std_logic_vector_tb;

architecture arch of tb_ieee_std_logic_vector_tb is

signal tb_indata_array : std_logic_vector( 0 to 7);

constant TB_CONST_ALL_1 : UNSIGNED ( 0 to 7) := ( others => '1' );

constant TB_MAX_LIMIT : integer := TO_INTEGER(TB_CONST_ALL_1);

signal tb_in1 : std_logic_vector( 3 downto 0 );

signal tb_in2 : std_logic_vector( 3 downto 0 );

signal tb_out1 : std_logic_vector( 3 downto 0 );

begin

tb_in1 <= tb_indata_array(0 to 3 );

tb_in2 <= tb_indata_array(4 to 7 );

inst : entity work.ieee_std_logic_vector port map

(in1 => tb_in1,

in2 => tb_in2,

out1 => tb_out1

);

process

variable seed1, seed2: positive;

variable rand: real;

variable int_rand: integer;

begin

loop

UNIFORM(seed1, seed2, rand);

int_rand := INTEGER(TRUNC(rand*(real(TB_MAX_LIMIT))));

tb_indata_array <= std_logic_vector(to_unsigned(int_rand,tb_indata_array'LENGTH));

wait for 5 ns;

end loop;

end process;

process( tb_in1,tb_in2,tb_out1)

variable var : line;

begin

write(var,string'("Time = "));

write(var,now);

write(var,string'(" in1 = "));

write(var,tb_in1);

write(var,string'(" in2 = "));

write(var,tb_in2);

write(var,string'(" out1 = "));

write(var,tb_out1);

writeline(OUTPUT,var);

end process;

end;

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