What Our Users Say

The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately and feel right at home. It was straightforward to quickly reproduce a module previously done with a Perl-to-Verilog utility that was hard to use and maintain. The support from Kanai is excellent. He responds quickly and is a pleasure to deal with. Nice work, Kanai!

Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. It's flexibility is a key reason we have chosen it for use in our Cloud-based platform.

If you are dealing with EDA research or tool development, I just can recommend trying the libraries and utilities provided by EDAUtils ( www.edautils.com). I am using their parser libraries (Verilog, VHDL) for more than three years now in my master's thesis and in several research projects. They also provide an SoC integration toolset (Baya) as well as an IP-XACT platform. So, if you are looking for well-supported EDA libraries, you may have a look at EDAUtils.

Kanai produced an excellent tool set, which is very useful for a complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by a high quality and ease of use. Bridgit IPXACT creator helps us to pack register, bus and module interfaces into a IEEE standard *.xml SPIRIT format to ensure high reusability in the future and protect our investments. I high recommend using Kanai’s products for every system-on-chip manufacturer and invest Venture Capital to support further improvement and commercialization.

Hi Kanai, thanks a lot for creating DesignPlayer and the huge java class lib behind. Even I discoverd only the tip of the iceberg, I got already a lot of my project done. I'm sure there is much more. Your strong support makes me confident to explore more details in future.

EDAUtils is one (if not the only one) of the most comprehensive tools for SoC design and integration and it is available for free. I included EDAUtils in the latest OpenTech Package as featured application among all free open source designs and tools and I believe with a lot of efforts it will grow to be one of the major tools in this domain.

thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.

Hi Kanai ,That really helped me now .. I got the job done at the right time ...

We were very pleased with your response. The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly. It was very easy to work with you and you delivered the translator super fast. Thanks for the great support!

We use the Verilog Parser for developing FPGA CAD Applications. The library is very stable and EDAUtils provided much helpful support to us!

... thanks - don't need anything else right now - thanks for your help getting this working.

Thanks for your quick answer. For the output, i think that GUI is not necessary. And if it's possible to have for each clock and reset ...

We have been using verilog testbench generator (http://www.edautils.com/VlogTBGen.html), Java version, in Unix. That is really usefull in coding process and easy to use. We got help from people of Edautils and it was fast and efficient. I would recommend their tools.

...I like the IP-XACT tools and others that you have developed. ... IP-XACT tools are a great ...

I used his VHDL Parser Library for my simple personal projects on vhdl code analysis. He is always open for propositions and always ready to get you good support.

The netlist parser provides a easy to use and flexible environment for developing my own custom analysis tools. The best part of the experience has been the prompt and helpful support.

I have tested the VHDL and Verilog RTL parsers API. I managed to make them work very easy on Ubuntu Linux. In my personal opinion, one can integrate the parsers in his Java project only by using the HDL logic and knowledge, without to much reading of the documentation, since the API is very intuitive and strait forward, supported by few very useful examples.

I downloaded and used verilog2vhdl translator from edautils. The tool is really amazing. Thanks a lot to Ghosh.

A tool verilog2vhdl is useful. It works properly in Windows too.

I downloaded and used Verilog2VHDL & VHDL2Verilog translator from EDAutils. The tool is really amazing. Thanks a lot to Ghosh.

I think this tool is one of its kind. Others are either expensive commercial tools or simple trash. ...

We are developing and using in our FPGA design practice open source tool, that provides HDL simulation directly in MATLAB and Simulink (http://code.google.com/p/vmodel/). Our tool is based on Verilator well-known open source simulator. And as Verilator out tool cannot simulate VHDL designs. But with vhdl2verilog translator we can solve this problems. Also I should mention EDAUtils support. They reply very fast and really try to help with your problem