This utility has been developed for those who want to convert VHDL design into Verilog. This tool supports almost the widely used VHDL constructs except Record and Physical type data. This has been developed in Java (1.8) in order to make it platform independent and bundled as an executable JAR file.

Usage

source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation directory )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation directory )
set PATH="%path%;%EDAUTILS_ROOT%\bin"
vhdl2verilog -in simple_and.vhd -top simple_and_top -out simple_and.v
OR
java com.eu.miscedautils.vhdl2verilog.vhdl2verilog -in simple_and.vhd -top simple_and -out output.v

You can provide multiple VHDL files even with wildcard like *.vhd through the -filelist switch. Also, you can exclude files with the -excludefilelist switch which also supports wildcards .

Get details by executing it as ' vhdl2verilog -help '

Send your feedback to help@edautils.com for further improvement of this tool.

Known Limitations:

1) Record data type

2) Physical data type- this type of construct is not synthesizable

3) NEXT and EXIT statements in sequential LOOP statements

4) Non-synthesizable constructs like allocator etc are not supported

5) Complex aggregate expression may not get translated properly

6) Behavioral constructs like WRITE, READ, TESTBENCH etc are not yet supported

Part of the EDAUtils toolset

Baya - AI-enabled SoC integration with IP-XACT and a 200+ command Tcl API
IP-XACT 1685 solution - component packaging, registers, memory maps and generators
RTL utilities - parsers, translators, testbench and document generators
Run online free - try this tool in the browser, no install

Download vhdl2verilog →

Trusted by design teams worldwide

The collection of tools and utilities fills a real void in EDA. The baya tool is exactly what we had been looking for to assemble large top-level modules in Verilog. The GUI and high-level TCL commands are intuitive, allowing designers to get started immediately.

Michael TrocinoIC Design Manager, Coherent Logix

Thanks for efficient tools which have been successfully used in our internal wireless design flow. Friendly support has been highly appreciated.

Claudine RaibautEDA Manager, Texas Instruments

Baya is a mature production quality tool with features and capabilities beyond those of tools provided by large EDA vendors. Its flexibility is a key reason we have chosen it for use in our Cloud-based platform.

David FritzCEO, Social Silicon

Kanai produced an excellent tool set, which is very useful for complex system-on-chip integration flows. We were skeptical in the beginning, but later got really impressed by the high quality and ease of use.

Boris V. KuznetsovCEO, SOCC

Thanks a lot for creating DesignPlayer and the huge Java class library behind it. Your strong support makes me confident to explore more details in future.

Rolf KemperManager, Mixed Signal Design, Renesas Electronics Europe

EDAUtils is one of the most comprehensive tools for SoC design and integration, and it is available for free. I included EDAUtils in the OpenTech Package as a featured application.

Jamil KhatibOpenTech Package

The VHDL2Verilog translator worked great, even handling the generate statements in the source VHDL. It met our needs exactly.

Jerry FrenkilVP of Engineering, NanoWatt Design

We use the Verilog Parser for developing FPGA CAD applications. The library is very stable and EDAUtils provided much helpful support to us.

Dustin PetersonUniversity of Tübingen

I like the IP-XACT tools and others that you have developed. The IP-XACT tools are great.

Amal KhailtashLead FPGA Designer, Ciena Communications

The netlist parser provides an easy to use and flexible environment for developing my own custom analysis tools. The best part has been the prompt and helpful support.

Gene Y. WuUniversity of Texas

We have been using the Verilog testbench generator in Unix. It is really useful in the coding process and easy to use. I would recommend their tools.

Lucas TeixeiraSMDH

That really helped me now. I got the job done at the right time.

S. KrishnanIntel