RTL Sorting

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This utility has been aimed for those designers who do not know the dependency of the VHDL / Verilog files in a given design nor they know which file to compile in which work library. This platform independent utility takes all the RTL files as input and then process those files internally and come up with a sorted/ordered list of files along with their proper VHDL /Verilog work library. The sorted output is written in the file sorted.out.list . It also creates modelsim and compilation scripts along with library mappings . The generated sorted.out.list file can be used to create compilation script for any VHD/Verilog tool. To run this tool goto to the installation area and source or execute the file setup_env file to setup the environment and then run it as -

Usage

source setup_env.('csh' or 'sh' or 'bat' as applicable )
Alternatively, for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( installation dir )
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014 ( installation dir )
set PATH="%path%;%EDAUTILS_ROOT%\bin"

sorthdlfiles -filelist infile.list

OR
java com.eu.miscedautils.SortHDL.SortHDL -filelist infile.list

You can list files with wild card as *.v* . Also, you can exclude files with the -excludefilelist switch, see the examples. This tool not only supports complex VHDL configuration and it also works fine even if the RTL has any syntax or semantic error(s).

See below one example command and output of this tool.

% sorthdlfiles -filelist infile.list -outfile modelsim_compile.csh

HDL Sort Utility

...

...

SortHDL: Note: Running with options : -filelist infile.list

SortHDL: Running with: -filelist infile.list

SortHDL: Note: Reading file : atom_config.vhd ...

SortHDL: Note: Reading input file atom_config.vhd ...

SortHDL: Note: Reading file : atom.vhd ...

SortHDL: Note: Reading input file atom.vhd ...

...

...

SortHDL: Note: Reading file : leaf.v ...

SortHDL: Readinf file leaf.v ...

SortHDL: Note: Reading file : grandleaf.v ...

SortHDL: Readinf file grandleaf.v ...

SortHDL: Note: Sorting files as per their expected compilation order ...

SortHDL: Note: Sorting is done ...

SortHDL: Sorted the HDL(s) successfully ...

SortHDL: Thank you for using this utility

SortHDL: Send your suggestion/feedback to help@edautils.com

SortHDL: Exiting ...

Output compile script

!/bin/csh -f

#########################################################

## This compile script has been generated with the free #

## RTL sorting tool called SortHDL from edautils.com #

## Contact help@edautils.com for any help/support #

## #

#########################################################

\mkdir -p OUTPUTDIR

set outdir=OUTPUTDIR

vlib dummylib

vmap dummylib $outdir/dummylib

vlib protonlib

vmap protonlib $outdir/protonlib

vlib packlib

vmap packlib $outdir/packlib

vlib neutronlib

vmap neutronlib $outdir/neutronlib

vlib WORK

vmap WORK $outdir/WORK

vlib vloglib

vmap vloglib $outdir/vloglib

vlib atomlib1

vmap atomlib1 $outdir/atomlib1

vcom -work dummylib electron.vhd

vcom -work protonlib proton_e.vhd

vcom -work protonlib proton_rtl.vhd

vcom -work packlib simplepackage_p.vhd

vcom -work packlib simplepackage_body.vhd

vcom -work neutronlib neutron.vhd

## Add +incdir+<path-of-include-dir> if required

vlog -work WORK grandleaf.v

## Add +incdir+<path-of-include-dir> if required

vlog -work vloglib leaf.v

vcom -work atomlib1 atom.vhd

vcom -work atomlib1 atom_config.vhd

vcom -work WORK molecule.vhd

vcom -work WORK molecule_cfg_block.vhd

vcom -work WORK molecule_cfg.vhd

Content of the input file

atom_config.vhd

atom.vhd

electron.vhd

molecule_cfg_block.vhd

molecule_cfg.vhd

molecule.vhd

neutron.vhd

proton_e.vhd

proton_rtl.vhd

leaf.v

grandleaf.v

simplepackage_body.vhd

simplepackage_p.vhd